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| part number 460gt revision 1.07 ? may 29, 2008 amcc proprietary 1 460gt powerpc 460gt embedded processor preliminary data sheet features ?powerpc ? 440 processor operating between 667mhz and 1ghz with 32kb i-cache and d- cache and 256kb l2/sram with parity checking ? on-chip memory (64kb) ? processor local bus (plb) with 128-bit width ? floating point unit ? double data rate 2/1 (ddr2/1) synchronous dram (sdram) interface ? one four-channel dma (direct memory access) for internal and external peripherals ? one single-channel, high-performance dma for internal use ? external 32-bit peripheral bus (ebc) for up to six devices. up to 100mhz ? programmable interrupt controller (uic) with up to 16 external interrupts ? programmable general purpose timers (gpts) ? two pci express 1.1 interfaces?one 4-lane and one 1-lane ? pci v2.3 interface. thirty-two bits at up to 66mhz ? four ethernet 10/100/1000mbps half- or full- duplex interfaces. operational modes supported are mii, rmii, gmii, rgmii, and sgmiii with qos, jumbo frames, interrupt coalescing, and tcp/ip acceleration ? up to four serial (uart) ports (16750 compatible) ? two iic interfaces (one with boot parameter read capability) ? nand flash interface ? spi interface ? serial rapid i/o (srio) port ? general purpose i/o (gpio) interface ? jtag interface for board level testing ? boot from pci memory, nor flash on the external peripheral bus, or nand flash on the nand flash interface ? optional security feature (ppc460gt-s) with kasumi. ? available in rohs comp liant, lead-free package description designed specifically to address high-end embedded applications, the powerpc 460gt (ppc460gt) provides a high-performance, low-power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. this chip contains a high-performance risc processor, a floating point unit, on-chip memory, a ddr2/1 sdram controller, pci and pci express bus interfaces, control for exte rnal rom and peripherals, dma with scatter/gather support, ethernet ports, serial ports, iic interfaces, spi interface, nand flash interface, srio support, an optional security feature with kasumi (ppc460gt-s), and general purpose i/o. technology: cmos cu-08, 90nm. package: 35mm, 728-ball thermally and electrically enhanced plastic ball grid array (te-epbga). rohs compliant package available. typical power: less than 6w at 1ghz. supply voltages required: 3.3v, 2.5v (ddr1, ethernet), 1.8v (ddr2), 1.2v.
460gt ? ppc460gt embedded processor preliminary data sheet 2 amcc proprietary revision 1.07 ? may 29, 2008 contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 powerpc 440 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 floating point unit (fpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 l2 cache/sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 security function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pci controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pci express controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ddr2/1 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dma 4-channel controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 serial ports (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 iic bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 serial peripheral controller (spi/scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 nand flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ddr2/1 sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 3 preliminary data sheet figures figure 1. order part number key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. ppc460gt functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. 35mm, 728-ball te-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 5. input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 6. output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 7. input setup and hold timing waveform for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 8. output delay and hold timing wave form for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 9. ddr sdram simulation signal termin ation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 10. ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 12. ddr sdram memory data and dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 13. ddr sdram read cycle timing?example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 tables table 1. system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 7. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 9. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 10. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 11. typical dc power supply requirem ents using ddr2 memory . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 12. typical dc power supply requirem ents using ddr1 memory . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 13. v dd supply power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 14. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 15. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 16. clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 17. peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 18. i/o specifications?all speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 19. i/o specifications?400mhz to 1000mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 20. ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 21. ddr sdram write operatio n conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 22. i/o timing?ddr sdram t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 23. i/o timing?ddr sdram t sa , and t ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 24. i/o timing?ddr sdram write timing t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 25. i/o timing?ddr sdram read timing t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 26. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 460gt ? ppc460gt embedded processor preliminary data sheet 4 amcc proprietary revision 1.07 ? may 29, 2008 ordering and pvr information for information on the availability of the following parts, contact your lo cal amcc sales office. for additional information on the part number structure see figure 1 . each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniq uely identifies the part. refer to the powerpc 460gt embedded processor user?s manual for details on accessing these registers. figure 1. order part number key product name order part number (see notes ) package revision level pvr value jtag id ppc460gt ppc460gt-spafff(f)t 35mm 728- ball te-epbga a 0x130218a0 0x144101e1 ppc460gt ppc460gt-npafff(f)t 35mm 728- ball te-epbga a 0x130218a1 0x144101e1 notes: characters following the dash (-): 1. s = security feature present, n = security feature not present 2. p = package type: u = lead-free (rohs compliant), t = contains lead. 3. a = chip revision level a 4. fff(f) = processor frequency: fff = 600 = 667mhz, fff = 800 = 800mhz, ffff = 1000 = 1ghz 5. t = case temperature range of ? 40 c to +85 c. amcc part number ppc460gt-sua1000t package processor frequency case temperature range revision level security feature note: the example p/n above contains the security feature, is lead-free, is capable of running at 1ghz, and is shipped in a tray (tape-and-reel pa ckaging is not available). 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 5 preliminary data sheet block diagram figure 2. ppc460gt functional block diagram the ppc460gt is a system on a chip (soc). processor core dcr bus 32kb on-chip peripheral bus (opb) - 32 bits, 100 mhz gpio dma processor local bus (plb) - 128 bits, 200 mhz external bus controller clock control reset power mgmt jtag trace timers mmu cntrlr opb arb d-cache 32kb i-cache (4-ch) sram cntrlr ppc440 ethernet 1000 x2 dcrs zmii rgmii 256kb l2 cache 10/100/ tah/qos 10/100/ 1000 x2 bridge x2 bridge uart x4 iic(x2) bsc spi nand flash controller mal w/ int. coalescing pci-express memory pci-e1 pci-e0 queue pci 4 lanes 32-bit 64+8 ddr 1 and 2 sdram cntrlr 33/66 mhz m0 m1 m4 m6 m10 arb s3 s4 m2 m3 s1 s3 m5 low latency (ll) segment high bandwidth (hb) segment int hand s2 s0 s0 srio (x1) (x4) hss x1/x4 1 lane hss x1 ocm 64kb s2 s7 trng/ pka s5 m7 s1 hsdma cntrlr bridge m8 s4 m9 gpt security engine w/kasumi external 16 interrupts uic sgmii x3 sn = slave n mn = master n fpu 460gt ? ppc460gt embedded processor preliminary data sheet 6 amcc proprietary revision 1.07 ? may 29, 2008 address maps the ppc460gt incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of various address regions which the processor can access. the second is the dcr address map for devi ce configuration registers (dcrs). the dcrs are accessed by software running on the ppc460gt processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (part 1 of 3) function sub function start address end address size local memory (ll) 1 ddr sdram 0000 0000 0000 0000 0000 0003 ffff ffff 16gb sram (l2 cache) 0000 0004 0000 0000 0000 0004 0003 ffff 256kb on-chip memory (ocm) 0000 0004 0004 0000 0000 0004 0004 ffff 64kb reserved 0000 0004 0005 0000 0000 0004 000f ffff 704kb internal plb interfaces (ll) 1 i2o/dma 0000 0004 0010 0000 0000 0004 0010 ffff 64kb i2o registers 0000 0004 0010 0000 0000 0004 0010 00ff 256b reserved 0000 0004 0010 0100 0000 0004 0010 01ff 256b hsdma registers 0000 0004 0010 0200 0000 0004 0010 02ff 256b reserved 0000 0004 0010 0300 0000 0004 0010 ffff 63.25kb pka & trng (eippkp) 0000 0004 0011 0000 0000 0004 0011 ffff 64kb reserved 0000 0004 0012 0000 0000 0004 0017 ffff 384kb security function (eip94) 0000 0004 0018 0000 0000 0004 001f ffff 512kb reserved 0000 0004 0020 0000 0000 0004 bfff ffff ~3gb 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 7 preliminary data sheet internal opb peripherals (ll) ebc memory except bank 0 6 0000 0004 c000 0000 0000 0004 e7ff ffff 640mb reserved 0000 0004 e800 0000 0000 0004 ef5f ffff 118mb general purpose timer 0000 0004 ef60 0000 0000 0004 ef60 01ff 512b reserved 0000 0004 ef60 0200 0000 0004 ef60 02ff 256b uart0 0000 0004 ef60 0300 0000 0004 ef60 0307 8b reserved 0000 0004 ef60 0308 0000 0004 ef60 03ff 248b uart1 0000 0004 ef60 0400 0000 0004 ef60 0407 8b reserved 0000 0004 ef60 0408 0000 0004 ef60 04ff 248b uart2 0000 0004 ef60 0500 0000 0004 ef60 0507 8b reserved 0000 0004 ef60 0508 0000 0004 ef60 05ff 248b uart3 0000 0004 ef60 0600 0000 0004 ef60 0607 8b reserved 0000 0004 ef60 0608 0000 0004 ef60 06ff 248b iic0 0000 0004 ef60 0700 0000 0004 ef60 071f 32b reserved 0000 0004 ef60 0720 0000 0004 ef60 07ff 224b iic1 0000 0004 ef60 0800 0000 0004 ef60 081f 32b reserved 0000 0004 ef60 0820 0000 0004 ef60 08ff 224b spi 0000 0004 ef60 0900 0000 0004 ef60 090f 16b reserved 0000 0004 ef60 0910 0000 0004 ef60 09ff 240b opb arbiter 0000 0004 ef60 0a00 0000 0004 ef60 0a3f 64b reserved 0000 0004 ef60 0a40 0000 0004 ef60 0aff 192b gpio0 controller 0000 0004 ef60 0b00 0000 0004 ef60 0b7f 128b reserved 0000 0004 ef60 0b80 0000 0004 ef60 0bff 128b gpio1 controller 0000 0004 ef60 0c00 0000 0004 ef60 0c7f 128b reserved 0000 0004 ef60 0c80 0000 0004 ef60 0cff 128b ethernet phy zmii 0000 0004 ef60 0d00 0000 0004 ef60 0d0f 16b reserved 0000 0004 ef60 0d10 0000 0004 ef60 0dff 240b emac0 controller 0000 0004 ef60 0e00 0000 0004 ef60 0eff 256b emac1 controller 0000 0004 ef60 0f00 0000 0004 ef60 0fff 256b reserved 0000 0004 ef60 1000 0000 0004 ef60 10ff 256b emac2 controller 0000 0004 ef60 1100 0000 0004 ef60 11ff 256b emac3 controller 0000 0004 ef60 1200 0000 0004 ef60 12ff 256b tahoe0 accelerator 0000 0004 ef60 1300 0000 0004 ef60 13ff 256b tahoe1 accelerator 0000 0004 ef60 1400 0000 0004 ef60 14ff 256b rgmii0 controller 0000 0004 ef60 1500 0000 0004 ef60 150f 16b reserved 0000 0004 ef60 1510 0000 0004 feff ffff 240b rgmii1 controller 0000 0004 ef60 1600 0000 0004 ef60 160f 16b table 1. system memory address map (part 2 of 3) function sub function start address end address size 460gt ? ppc460gt embedded processor preliminary data sheet 8 amcc proprietary revision 1.07 ? may 29, 2008 reserved 0000 0004 ef60 1610 0000 0004 feff ffff 262b boot rom 2, 3 ebc memory bank 0 0000 0004 ff00 0000 0000 0004 ffff ffff 16mb internal plb interfaces (ll) reserved 0000 0005 0000 0000 0000 0007 ffff ffff 12gb local memory alias (hb) aliased ddr sdram 0000 0008 0000 0000 0000 000b ffff ffff 16gb pci/pcie space (hb) pci express and srio memory 0000 000c 0000 0000 0000 000c 07ff ffff 128mb pci i/o 0000 000c 0800 0000 0000 000c 0800 ffff 64kb pc express and srio memory 0000 000c 0801 0000 0000 000c 087f ffff ~8mb pci extra i/o 0000 000c 0880 0000 0000 000c 0bff ffff ~56mb pci express memory and srio memory 0000 000c 0c00 0000 0000 000c 0ebf ffff ~44mb pci configuration registers 0000 000c 0ec0 0000 0000 000c 0ec0 0007 8b reserved 0000 000c 0ec0 0008 0000 000c 0ec7 ffff ~512kb pci local registers 0000 000c 0ec8 0000 0000 000c 0ec8 11ff 4.75kb reserved 0000 000c 0ec8 1200 0000 000c 0ecf ffff ~512kb pci special cycle 0000 000c 0ed0 0000 0000 000c 0ed0 0003 4b reserved 0000 000c 0ed0 0004 0000 000c 0fff ffff ~19mb pci express interrupt handler 0000 000c 1000 0000 0000 000c 1000 00ff 256b pci, pci-e and srio memory 0000 000c 1000 0100 0000 000c feff ffff ~3.8mb pci boot rom (pci memory) 0000 000c ff00 0000 0000 000c ffff ffff 16mb pci, pci-e and srio memory 0000 000d 0000 0000 0000 000f ffff ffff 12gb reserved 4 0000 0010 0000 0000 03ff ffff ffff ffff reserved 5 0400 0000 0000 0000 0fff ffff ffff ffff xor space (hb) xor 1000 0000 0000 0000 1fff ffff ffff ffff pci/pcie space (hb) pci, pci-e and srio memory 2000 0000 0000 0000 ffff ffff ffff ffff notes: 1. ddr sdram, sram (l2 cache) and on-chip memory (ocm) can be located anywhere in the local memory area of the memory map. 2. the boot rom area of the memory map are intended for use by rom or flash-type devices. while locating volatile ddr sdram and sram in this region is supported, use of t hese regions for this purpose is not recommended. 3. when the optional boot from pci memory is selected, the pci boot rom address space begins at 0000 000c ff00 0000 (16 mb). 4. never decoded. 5. unpredictable results on read and write operations. 6. accessed by means of ebc peripheral bank configuration registers. table 1. system memory address map (part 3 of 3) function sub function start address end address size 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 9 preliminary data sheet table 2. dcr address map function base address start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b 12w clocking power on reset (cpr) 00 0000 110x 00c 00d 2w system dcrs (sdr) 00 0000 111x 00e 00f 2w memory controller 00 0001 000x 010 011 2w external bus controller (ebc) 00 0001 001x 012 013 2w reserved 014 01f 12w l2 cache as sram 00 0010 xxxx 020 02f 16w l2 controller 00 0011 xxxx 030 03f 16w memory queue 00 010x xxxx 040 04f 16w reserved 050 05f 16w i2o/dma controller 00 011x xxxx 060 07f 32w plb arbiter 00 1000 xxxx 080 08f 16w plb-to-opb bridge 00 1001 xxxx 090 09f 16w reserved 0a0 0af 16w on-chip memory (ocm) 00 1011 xxxx 0b0 0bf 16w universal interrupt controller 0 00 1100 xxxx 0c0 0cf 16w universal interrupt controller 1 00 1101 xxxx 0d0 0df 16w universal interrupt controller 2 00 1110 xxxx 0e0 0ef 16w universal interrupt controller 3 00 1111 xxxx 0f0 0ff 16w pci express 0 01 000x xxxx 100 11f 32w pci express 1 01 001x xxxx 120 13f 32w srio 01 010x xxxx 140 15f 32w power management 01 011x xxxx 160 167 8w reserved 168 17f 24w ethernet mal 01 1xxx xxxx 180 1ff 128w dma controller 10 00xx xxxx 200 23f 64w reserved 240 3ff 448w notes: 1. dcr addresses are 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register. one kiloword (1024w) equals 4kb (4096 b). 460gt ? ppc460gt embedded processor preliminary data sheet 10 amcc proprietary revision 1.07 ? may 29, 2008 powerpc 440 processor the powerpc 440 processor (in 90nm technology) is de signed for high-end applications: raid controllers, san, iscsi, routers, switches, printers, set-top boxes, and so on. it implements the book e powerpc embedded architecture and uses the 128-bit version of ibm?s on-chip coreconnect bus architecture. features include: ? up to 1ghz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache ? utlb word wide parity on data and tag address parity with exception force ? three logical regions in d-cache: locked, transient, normal ? d-cache full line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? 7-stage pipeline ? three execution pipelines ? dynamic branch prediction ? memory management unit ? 64-entry, full associative, unified tlb with optional parity ? separate instruction and data micro-tlbs ? storage attributes for write-through, cache- inhibited, guarded, and big or little endian ? debug facilities ? multiple instruction and data range breakpoints ? data value compare ? single step, branch, and trap events ? non-invasive real-time trace interface ? 24 dsp instructions ? single cycle multiply and multiply-accumulate ? 32 x 32 integer multiply ? 16 x 16 -> 32-bit mac floating point unit (fpu) the chip has a built-in super scalar fp u that supports both single- and double-precision operations, and offers single cycle through put on most instructions. features include: ? five stages with 2 mflops/mhz ? hardware support for ieee 754 ? single- and double-precision ? single-cycle throughput on most instructions ? thirty-two 64-bit floating point registers l2 cache/sram the ppc460gt also provides a 256kb l2 cache between the processor local bus and the processor?s d- and i-caches. this memory unit can be alternatively programmed to function as 256kb of sram. features include: ? four banks of 64kb each ? memory cycles supported: ? single beat read and write, 1 to 16 bytes ? quadword read and write burst for 12-bit master ? guarded memory accesses on 4kb boundaries 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 11 preliminary data sheet ? sustainable 3.2gb/s peak bandwidth at 200mhz ? use as an l2 cache improves proces sor performance and reduces the plb load ? data array and tag array parity ? unified data and instruction cache ? four-way set associative ? 36-bit addressing ? full lru replacement algorithm ? write through, look aside on-chip memory (ocm) the ppc460gt provides 64kb of on-chip memory. features include: ? up to 128-bit bus width ? 128-bit slave attachment, addressable by any plb master ? transfers by plb slave cycles: ? single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters) ? 4- and 8-word line reads and writes ? double word read and write bursts for 64-bit masters ? quadword read and write bursts for 128-bit masters ? slave-terminated double word a nd quadword fixed length bursts ? master-terminated variable length bursts ? guarded memory access on 4kb boundaries ? data parity checking ? data transfers at plb bus speeds ? power management ? use as storage area for dma descriptors and packet data for processing by ethernet and security function. internal buses the powerpc 460gt features three standard internal buses: one processor local bus (plb), one on-chip peripheral bus (opb), and the device control register bus (dcr). the high performance, high bandwidth functions such as the powerpc 440 processor, the ddr sdram memory controller, pci express, and pci connect to the plb. the opb hosts lower data rate peripherals. the daisy-chai ned dcr provides a lower bandwidth path for passing status and control information between the processor and the other on-chip cores. the plb has a crossbar arbiter that supports data tran sfer between the plb master and two slave segments identified as the low latency (ll) and high bandwidth (h b) segments. the ll segment allows plb masters cpu and i2o, that are adversely affected by latency, to co mmunicate with slave devices wit h minimal latency. the hb segment allows plb masters dma, pci and pci express to exchange large blocks of data with sdram, pci and pci express without interfering wit h the low latency plb masters. features include: ? plb4 (128-bit) ? 128-bit implementation of the plb architecture ? separate and simultaneous read and write data paths ? 64-bit address ? simultaneous control, address, and data phases ? four levels of pipelining ? byte-enable capa bility supporting unaligned transfers ? 32- and 64-byte burst transfers ? 200mhz, maximum 12.8gb/s (simultaneous read and write) ? processor:bus clock ratios of n:1 460gt ? ppc460gt embedded processor preliminary data sheet 12 amcc proprietary revision 1.07 ? may 29, 2008 ?opb ? 32-bit data path with dynamic sizing for 32-, 16-, and 8-bit width ? 32-bit address ?100mhz ? dcr ? 32-bit data path ? 10-bit address security funct ion (optional) the built-in security function (ppc460gt-s only) is a cryp tographic engine attached to the plb with built-in dma and interrupt controllers. features include: ? federal information processing standard (fips) 140-2 design ? support for an unlimited number of security associations (sa) ? different sa formats for each supported protocol (ipsec/ssl/tls/srtp) ? internet protocol security (ipsec) features ? full packet tran sforms (esp & ah) ? complete header and trailer processing (ipv4 and ipv6) ? multi-mode automatic padding ? "mutable bit" handler for ah, including ipv4 option and ipv6 extension headers ? secure socket layer (ssl) and transport layer security (tls) features ? packet transforms ? one-pass hash-then-encrypt for ssl and tls packet transforms for inbound packet using stream cipher ? secure real-time protocol (srtp) features ? packet transforms ? roc removal and tag insertion ? variable bypass offset of header length per packet ? ipsec/ssl security acceleration engine ? des, 3des, aes, arc-4, aes-gc m, and gmac-aes encryption ? md-5, sha-1, and sha-256 hashing, hmac encrypt-hash and hash-decrypt ? kasumi algorithm support ? public key acceleration for rsa, dsa and diffie-hellman ? true or pseudo random number generators ? non-deterministic true random numbers ? pseudo random numbers with lengths of 8b or 16b ? ansi x9.17 annex c compliant using a des algorithm ? interrupt controller ? fifteen programmable, maskable interrupts ? initiate commands via an input interrupt ? sixteen programmable interrupts indicating completion of certain operations ? all interrupts mapped to one level- or edge-sensitive programmable interrupt output ? dma controller ? autonomous, 4-channel ? 1024-words (32 bits/word) per dma transfer ? scatter/gather capability wit h byte aligned addressing 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 13 preliminary data sheet pci controller the pci interface allows connection of pci devices to th e powerpc processor and local memory. this interface is designed to version 2.3 of the pci specif ication and supports 32- bit pci devices. reference specifications: ? pci specification version 2.3 ? pci bus power management interface specification version 1.1 features include: ? frequency to 66mhz ? 32-bit bus ? pci host bus bridge or an adapter device's pci interface ? internal pci arbitration function, supporting up to four external devices, that can be disabled for use with an external arbiter ? support for inbound and outbound message signaled interrupts (msi) ? simple message passing capability ? asynchronous to the plb ? pci power management 1.1 ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci bus memory ? error tracking/status ? supports initiation of transfers of the following types: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles ? vital product data (vpd) support pci express controller there are two independent pci express interfaces compliant with pci expr ess base specification 1.1. one interface can be configured as one to four lanes while th e other functions as one-lane only. the four-lane interface shares a high-speed serdes with the serial rapid i/o (sri o) interface. both can be root or endpoint ports. features include: ? two independent pci express interfaces ? one 4 lanes ? one 1 lane ? 2.5 gb/sec full duplex per lane ? compliant with pci express base specification 1.1 ? each pci express port can be end point or root complex. (upstream & downstream) ? applications compliant with msi rules are limited to one endpoint port per ppc460gt ? power management ? supports one virtual channel (vc0) no traffic class (tc) filtering ? maximum payload block size 512 bytes ? supports up to 512 bytes maximum read request size ? requests supported: ? up to 4 (x4) or 2 (x1) posted outbound write requests (memory and messages) ? up to 4 (x4) or 2 (x1) posted inbound write requests ? up to 4 (x4) or 2 (x1) outbound read requests outstanding on pci express ? up to 4 (x4) or 2 (x1) inbound read requests outstanding on pci express ? outbound i/o request as a pci express root port ? inbound i/o request as a pci express endpoint 460gt ? ppc460gt embedded processor preliminary data sheet 14 amcc proprietary revision 1.07 ? may 29, 2008 ? buffering in each pci express port for the following transaction types: ? 2kb replay buffer: up to 4 in flight transactions ? 2kb (x4) or 1kb (x1) for outbound posted writes ? 2kb (x4) or 1kb (x1) for outbound reads completion ? 2kb (x4) or 1kb (x1) for inbound posted writes ? 2kb (x4) or 1kb (x1) for inbound reads completion ? parity checking on each buffer ? programmable outbound memory (pom) regions: 3 memo ry, 1 i/o, 1 message, 1 configuration, 1 internal register ? programmable inbound memory (pim) regions: 4 memory, 1 i/o, 1 expansion rom ? intx interrupts support (legacy pci): ? up to four intx termination for root port s. a/b/c/d interrupts are wired to the uic ? a/b/c/d intx types generation for endpoints ? msi - message signaled interrupts ? msi generation for endpoint ? msi termination for root ports ? msi_x terminatio n for root ports ddr2/1 sdram memory controller the double data rate 2/1 (ddr2/1) sdram memory cont roller supports industry standard 184-pin dimms, so- dimms, and other discrete devices. globa l memory timings, address and bank sizes, and memory addressing modes are programmable. this controller interfaces to the plb through a memory queue (mq) function that includes six high-speed 1kb fifo buffers. the correct i/o supply voltage must be provided for the two types of ddr devices: ddr1 devices require +2.5v and ddr2 devices require +1.8v. features include: ? registered and non-registered industry standard dimms ? ddr2 333/400 support ? 64-and 32-bit memory interfaces with optional 8-bit ecc (sec/ded) ? 3.2gb/s peak bandwidth for the 64-bit interface ? 1.6gb/s peak bandwidth for the 32-bit interface ? four chip (bank) select signals supporting four external banks ? cas latencies of 2, 3, 4, 5, 6, and 7 ? page mode accesses (up to 32 open pages) with configurable paging policy ? look-ahead request queue with programmable depth of four commands ? optional optimized command scheduling (activate/precharge non- conflicting banks while accessing the current bank) ? up to 16gb in four external banks ? up to two memclkout signals ? programmable address mapping and timing ? hardware and software initiated self-refresh ? sync dram configuration by means of mode register and extended mode register set commands ? power management (self-refresh, suspend, sleep) ? low latency and high bandwidth plb ports ? selectable plb read response (immediate or deferred) ? programmable low latency and high bandwidth arbitration schemes ? high bandwidth port has four 1kb read buffers and two 1kb write buffers ? low latency port has four 128b read buffers and two 128b write buffers 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 15 preliminary data sheet external peripheral bus controller (ebc) the external bus controller (ebc) transfers data betwee n the plb and external memory or peripheral devices attached to the external peripheral bus. the ebc allows for direct attachment of me mory devices such as rom and sram, dma device-paced memory devices, and dma peripheral devices. features include: ? up to six rom, eprom, sram, flash memory , and slave peripheral i/o banks supported ? up to 100mhz operation ? burst and non-burst devices ? 32-bit byte-addressable data bus ?data parity ? 27-bit address ? peripheral device pacing with external ready ? latch data on ready, synchronous or asynchronous ? programmable access timing per device ? 256 wait states for non-burst ? 32 burst wait states for first access and up to eight wait states for subsequent accesses ? programmable cson, csoff relative to address ? programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping ? external dma slave support ethernet controller four 10/100/1000 ethernet ports are supported. features include: ? compliant with ansi/i eee standard 802.3 and ieee 802.3u supplement ? compliant with ieee standar d 802.3z (gigabit ethernet) ? four 10/100/1000 interfaces running in full- and half-duplex modes providing: ? two gigabit media independent interface (gmii) ? two media independent interface (mii) ? four reduced media independent interface (rmii) ? four serial mii (smii) at 100/10mbps. ? four reduced gigabit mii (rgmii) ? three serial gigabit media independent interface (sgmii). ? quality of service (qos) support on two interfaces ? support of ieee 802.1p priority queueing for up to 8 priorities ? recognizes tci field in vlan-tagged fram es where the priority field is coded ? jumbo frame support (9018 bytes) ? support for ethernet ii formatted frames (rfc894) ? support for ieee form atted frames (rfc1042) ? handles vlan-tagged frames (ieee 802.2ac) ? tcp/ip acceleration hardware (tah) support on two interfaces ? off loads gigabit ethernet protocol processing from the cpu ? checksum verification for tcp/udp/ip headers in the receive path ? checksum generation for tcp/udp/ ip headers in the transmit path ? tcp segmentation support in the transmit path ? ipv4 and ipv6 support ? ipv6 header extension support ? wake on lan handling ? 256-bit hash table to filter multicast frames ? dma capability 460gt ? ppc460gt embedded processor preliminary data sheet 16 amcc proprietary revision 1.07 ? may 29, 2008 ? interrupt coalescence dma 4-channel controller the 4-channel dma controller provides a dma interface between the plb memories and internal and external peripheral devices. features include: ? supports the following transfers: ? memory-to-memory ? buffered peripheral to memory ? buffered memory to peripheral ? scatter/gather capability for pr ogramming multiple dma operations ? 8-, 16-, 32-bit peripheral support (opb and external) ? 64-bit addressing ? 128 byte fifo buffer ? address increment or decrement ? support for: ? internal and external peripherals ? memory mapped peripherals ? peripherals running on slower frequency buses serial rapid i/o (srio) the serial rapid io (srio) interface provides an interf ace to physical storage devices. it shares the high-speed serdes with the 4-lane pci-express interface. features include: ? compliant with rapidio interconnect specification, revision 1.2 ? supports operation at 1.25 gbps, 2.50 gbps, and 3.125 gbps ? supports 1x/4x lp-serial implementation of rapidio (except gsm extensions) ? supports rapidio multicast event (tod) reception and transmission ? supports rapidio error management extensions and software error recovery ? supports interoperability class 3 (complex mastering device) ? supports device hot-insertion/extraction ? separate 4kb transmit and receive request/response queues i20/dma controller the i2o/dma controller provides one high speed dma (hsdma) interface to the plb and support for i2o messaging. the hsdma provides single-channel direct memory access support to ease the cpu burden. i2o manages message frame address (mfa) fifos or queues in memory in response to i2o register reads and writes and transfers message frames. dma features include: ? programmable command pointer fifo and completion fifo size (up to 2048 dma operations queued) ? separate 512-byte buffering for transmit and receive ? 1.4gb throughput (local read) ? 1.0gb throughput (remote read) ? simultaneous fill and drain (plb read/write pipelining) ? any source plb address to any destination address ? no memory alignment restrictio ns on source or destination ? 32-byte command descriptor block ? maximum transfer size of 16mb ? 64-bit addressing 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 17 preliminary data sheet ? prefetch indicators fo r pci buffer management ? supports initiation of transfer to the following address spaces: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles ? iscsi crc32 generation and checking i2o features include: ? i2o pull- and push-messaging methods ? dynamic message frame size ? programmable fifo size (4096 64-bit mfas maximum) ? 64- and 32-bit mfa sizes ? three interrupt gathering methods ? registered mfa prefetch and posting ? 32-bit inbound and outbound doorbell registers ? four 32-bit scratch pad registers serial ports (uart) the universal asynchronous receiver/transmitter (uart) interface provides one 8-signal port, or two 4-signal ports, or four 2-signal ports. the uart performs serial-to- parallel conversion on data received from a peripheral device or a modem, and parallel-to-serial conversion on data received from the processor. features include: ? up to four ports in th e following combinations: ? one 8-pin (uart0) ? two 4-pin (uart0 and uart1) ? four 2-pin (uart0, uart1, uart2, and uart3) ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility with 16750 register set ? complete status reporting capability ? fully programmable serial-i nterface characteristics ? supports dma using the 4-channel internal dma function ? 64-byte fifos for buffering transmit and receive data 460gt ? ppc460gt embedded processor preliminary data sheet 18 amcc proprietary revision 1.07 ? may 29, 2008 iic bus controller the inter-integr ated circuit (iic) interface provides a philips ? i 2 c ? compatible interface operating up to 400 khz either as a master, a slave, or both, with a bootstrap co ntroller (bsc) included. during chip reset, the bootstrap controller can read configuration data from an iic-compa tible memory device (for ex ample, eeprom). this data can be used to replace the default conf iguration settings provided by the chip. features include: ? two iic interfaces ? support for philips semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully prog rammable configuration registers ? one programmable interrupt request signal ? provides full management of all iic bus protocols ? programmable error recovery ? port 0 includes an integrated bsc that supports a serial bootstrap rom with default override parameters at initialization serial peripheral co ntroller (spi/scp) the serial peripheral interface (also known as the seri al communications port) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. the spi is a master on the serial port supporting a 3-wire interface (receive , transmit, and clock), and is a slave on the opb. features include: ? three-wire serial port interface ? full-duplex synchronous operation ? spi bus master ? programmable clock rate divider ? clock inversion ? reverse data ? local data loop back for test nand flash controller the nand flash controller provides a simple interface be tween the ebc and up to four separate external nand flash devices. it provides both direct command, address, an d data access to the external device as well as a memory-mapped linear region that generates data access es. nand flash data is transferred on the peripheral data bus. features include: ? one to four banks supported on ebc ? direct interface to: ? discrete nand flash devi ces (up to four devices) ? smartmedia card socket (22-pins) ? device sizes: ? 4mb and larger supporte d for read/w rite access ? 4mb to 256mb supported for boot-from-nand fl ash (size supported depends on addressing mode) 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 19 preliminary data sheet ? (512 + 16)-b or (2k + 64)-b page sizes supported ? boot from nand supported with execution of up to 4kb of boot code out of block 0 ? ecc provides single-bit error correction and double-bit error detection in each 256b of stored data ? chip select pins are multiplexed with ebc general purpose timers (gpt) provides a separate time base counter and additional system timers in addition to those defined in the processor. features include: ? time base counter (32 bits) driven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller controller functions and gpio registers are programm ed and accessed by means of memory-mapped opb bus master accesses. features include: ? sixty-four gpios multiplexed with othe r functions. dcrs control whether a gpio pin acts as a gpio or is used for another purpose. ? each gpio output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). universal interrupt controller (uic) universal interrupt controllers (uics) provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip powerpc processor. note: processor specific interrupts (for exam ple, page faults) do not use uic resources. features include: ? sixteen external interrupts ? edge triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to the on-chip processor ? programmable interrupt priority ordering ? programmable critical interrupt ve ctor for faster vector processing jtag features include: ? ieee 1149.1 test access port ? jtag boundary scan description language (bsdl) ? ibm riscwatch support refer to http://www.amcc.co m/embedded/partners for a list of amcc partners supplying probes for use with this port. 460gt ? ppc460gt embedded processor preliminary data sheet 20 amcc proprietary revision 1.07 ? may 29, 2008 package diagram figure 3. 35mm, 728-ball te-pbga package 35.0 gold gate release corresponds to pcb substrate mold compound a01 ball location top view bottom view notes: 1. all dimensions are in mm. 2. package is available with lead or 30 24 a 26 af b c d e f g h j k l m aa n p r t u v w y ab ac ad ae thermal balls 01 03 05 07 09 11 13 15 17 19 02 04 06 08 10 12 14 16 18 21 23 25 20 22 24 34 27 29 31 33 28 30 32 ap aj ag ah ak al am an 33.0 1.0 728 x 0.60 0.10 solder ball 7.0 2.65 max 0.4 - 0.6 3. package conforms to jedec ms-034. part lot number (zzzzz) lead-free (rohs compliant). side view typ typ logo view ppc460gt e1 1ywwbzzzzz ppc460gt-nprfff(f)t ? ccccccc number mmddql heat slug 4. optional solder ball diameter is 0.63 +0.07/ ? 0.13. 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 21 preliminary data sheet signal lists the following table lists all the external signals in alphab etical order and shows the ball (pin) number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. multiplexed signals appear alphabetically multiple times in the list? once for each signal name on the ball. the page number listed gives the page in table 7 on page 60 where the signals in the indicated interface group begin. in cases where signals in the same interface group (for exampl e, ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary mode name appearing first. in cases where the signals ha ve the same function but are associated with different ports (for example, uart), the signals are separated by a slash (/). these signals are listed only once, and appear alphabetically by the primary mode or primary port name. alphabetical signal list table 3. signals listed alphabetically (part 1 of 27) signal name ball interface group page agnd l01 power 69 agnd l02 agnd m04 agnd m06 agnd p03 agnd p04 agnd p06 agnd r01 agnd r02 agnd r06 agnd u01 agnd u04 agnd u05 agnd y01 agnd y03 agnd y05 agnd aa04 460gt ? ppc460gt embedded processor preliminary data sheet 22 amcc proprietary revision 1.07 ? may 29, 2008 av dd l03 power 69 av dd l06 av dd m03 av dd m05 av dd n03 av dd n06 av dd p05 av dd t03 av dd u02 av dd u03 av dd u06 av dd v03 av dd v06 av dd w03 av dd w06 av dd y02 av dd y04 av dd ab04 ba0 an32 ddr2/1 sdram 62 ba1 ap31 ba2 am31 banksel0 al28 ddr2/1 sdram 62 banksel1 ap29 banksel2 am29 banksel3 an29 cas al29 ddr2/1 sdram 62 clken0 ae29 ddr2/1 sdram 62 clken1 af34 clken2 ae33 clken3 ae31 [dmaack0]gpio47[peraddr06][irq14] c31 dma 66 [dmaack1]gpio44[percs4 ][irq11] e21 [dmaack2]gpio31[perpar1][irq8] a16 [dmaack3]gpio36[uart0cts ][uart3rx] e31 [dmareq0]gpio46[peraddr05][irq13] b32 [dmareq1]gpio43[percs3 ][nfce3 ][irq10] a22 [dmareq2]gpio30[perpar0][irq7] a20 [dmareq3]gpio33[perpar3][irq4] f13 table 3. signals listed alphabetically (part 2 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 23 preliminary data sheet dm0 p31 ddr2/1 sdram 62 dm1 u30 dm2 v30 dm3 ab34 dm4 am25 dm5 ap23 dm6 an20 dm7 am17 dm8 ad34 dqs0 p33 dqs0 p32 ddr2/1 sdram 62 dqs1 u32 dqs1 u31 dqs2 w31 dqs2 w32 dqs3 aa30 dqs3 aa31 dqs4 ap25 dqs4 an25 dqs5 an22 dqs5 am22 dqs6 am19 dqs6 al19 dqs7 ak17 dqs7 al17 dqs8 ad32 dqs8 ad33 e1ov dd y14 power 69 e1ov dd aa15 e1ov dd ad06 e1ov dd af02 e1ov dd ag05 e1ov dd aj11 e1ov dd ak02 e1ov dd ak08 e1ov dd an05 e1ov dd an09 e2ov dd ak13 power 69 e2ov dd an16 table 3. signals listed alphabetically (part 3 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 24 amcc proprietary revision 1.07 ? may 29, 2008 eagnd ap12 power 69 eavdd ap11 ecc0 ac31 ddr2/1 sdram 62 ecc1 ac30 ecc2 ae32 ecc3 ae34 ecc4 ac34 ecc5 ac32 ecc6 ad31 ecc7 ad30 [eot0/tc0]gpio48[peraddr07][irq15] d30 dma 66 [eot1/tc1]gpio45[percs5 ][irq12] d21 [eot2/tc2]gpio32[perpar2][irq9] a14 [eot3/tc3]gpio37[uart0rts ][uart3tx] d33 extreset f22 external peripheral 66 table 3. signals listed alphabetically (part 4 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 25 preliminary data sheet gmc0cd, gmc1rxclk, rmii1rxer ap05 ethernet 0 63 gmc0crs, gmc1txclk, rmii0crsdv al07 gmc0gtxclk, gmc0txclk an06 gmc0rxclk, gmc0rxclk am07 gmc0rxd0, gmc0rxd0, rmii0rxd0, smii0rxd al09 gmc0rxd1, gmc0rxd1, rmii0rxd1, smii1rxd ak09 gmc0rxd2, gmc0rxd2, rmii1rxd0, smii2rxd ap08 gmc0rxd3, gmc0rxd3, rmii1rxd1, smii3rxd aj09 gmc0rxd4, gmc1rxd0 an08 gmc0rxd5, gmc1rxd1 al08 gmc0rxd6, gmc1rxd2 am08 gmc0rxd7, gmc1rxd3 ap07 gmc0rxdv, gmc0rxctl, rmii1crsdv al06 gmc0rxer, gmc1rxctl, rmii0rxer aj10 gmc0txclk,, rmii01refclk, smiirefclk an04 gmc0txd0, gmc0txd0, rmii0txd0, smii0txd am02 gmc0txd1, gmc0txd1, rmii0txd1, smii1txd ak04 gmc0txd2, gmc0txd2, rmii1txd0, smii2txd al02 gmc0txd3, gmc0txd3, rmii1txd1, smii3txd al01 gmc0txd4, gmc1txd0 ak03 gmc0txd5, gmc1txd1 am01 gmc0txd6, gmc1txd2 ah05 gmc0txd7, gmc1txd3 al03 gmc0txen, gmc0txctl, rmii0txen, smiisync am05 gmc0txer, gmc1txctl, rmii1txen aj08 table 3. signals listed alphabetically (part 5 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 26 amcc proprietary revision 1.07 ? may 29, 2008 [gmc1cd, gmc3rxclk, rmii3rxer]gpio17 ag02 ethernet 1 64 [gmc1crs, gmc3txclk, rmii2crsdv]gpio20 ag03 [gmc1gtxclk, gmc2txclk] ae06 [gmc1rxclk, gmc2rxclk] af06 [gmc1rxd0, gmc2rxd0, rmii2rxd0]gpio08 ah04 [gmc1rxd1, gmc2rxd1, rmii2rxd1]gpio09 aj05 [gmc1rxd2, gmc2rxd2, rmii3rxd0]gpio10 ag06 [gmc1rxd3, gmc2rxd3, rmii3rxd1]gpio11 aj02 [gmc1rxd4, gmc3rxd0]gpio12 aj04 [gmc1rxd5, gmc3rxd1]gpio13 ah03 [gmc1rxd6, gmc3rxd2]gpio14 aj01 [gmc1rxd7, gmc3rxd3]gpio15 ah01 [gmc1rxdv, gmc2rxctll, rmii3crsdv]gpio21 ad04 [gmc1rxer, gmc3rxctl, rmii2rxer]gpio18 ag04 gmc1txclk, rmii23refclk ac06 [gmc1txd0, gmc2txd0, rmii2txd0]gpio00 ag01 [gmc1txd1, gmc2txd1, rmii2txd1]gpio01 ad05 [gmc1txd2, gmc2txd2, rmii3txd0]gpio02 ae04 [gmc1txd3, gmc2txd3, rmii3txd1]gpio03 af01 [gmc1txd4, gmc3txd0]gpio04 ae02 [gmc1txd5, gmc3txd1]gpio05 ae01 [gmc1txd6, gmc3txd2]gpio06 ab05 [gmc1txd7, gmc3txd3]gpio07 ad03 [gmc1txen, gmc2txctl, rmii2txen]gpio19 af03 [gmc1txer, gmc3txctl, rmii3txen]gpio16 af04 gmcmdclk aj03 ethernet 0 63 gmcmdio ak01 gmcrefclk ap09 table 3. signals listed alphabetically (part 6 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 27 preliminary data sheet gnd a01 power 69 gnd a02 gnd a03 gnd a33 gnd a34 gnd b01 gnd b02 gnd b03 gnd b07 gnd b12 gnd b23 gnd b28 gnd b33 gnd b34 gnd c01 gnd c02 gnd c03 gnd c16 gnd c32 gnd d04 gnd d31 gnd e05 gnd e10 gnd e23 gnd e25 gnd e28 gnd e30 gnd f06 gnd f16 gnd f19 gnd f29 gnd f30 gnd f31 gnd f32 table 3. signals listed alphabetically (part 7 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 28 amcc proprietary revision 1.07 ? may 29, 2008 gnd g02 power 69 gnd g31 gnd g33 gnd h01 gnd j01 gnd j03 gnd j30 gnd j32 gnd k02 gnd k05 gnd k06 gnd k30 gnd m30 gnd m33 gnd p14 gnd p16 gnd p19 gnd p21 gnd r15 gnd r16 gnd r19 gnd r20 gnd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t20 gnd t21 gnd t30 gnd u16 gnd u17 gnd u18 gnd u19 table 3. signals listed alphabetically (part 8 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 29 preliminary data sheet gnd v16 power 69 gnd v17 gnd v18 gnd v19 gnd w14 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 gnd w21 gnd w29 gnd y15 gnd y16 gnd y19 gnd y20 gnd aa14 gnd aa16 gnd aa19 gnd aa21 gnd ac01 gnd ac03 gnd ac04 gnd ac05 gnd ac33 gnd ad01 gnd ae03 gnd ae05 gnd ae30 gnd af05 gnd af29 gnd af30 gnd ag29 gnd ah02 gnd ah33 table 3. signals listed alphabetically (part 9 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 30 amcc proprietary revision 1.07 ? may 29, 2008 gnd aj06 power 69 gnd aj13 gnd aj16 gnd aj23 gnd aj25 gnd aj26 gnd aj27 gnd aj29 gnd aj30 gnd aj31 gnd ak05 gnd ak06 gnd ak07 gnd ak10 gnd ak14 gnd ak19 gnd ak24 gnd ak25 gnd ak28 gnd ak29 gnd ak30 gnd al04 gnd al05 gnd al22 gnd al25 gnd al30 gnd al31 gnd al32 gnd al33 gnd al34 gnd am03 gnd am04 gnd am06 gnd am10 gnd am30 gnd am32 table 3. signals listed alphabetically (part 10 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 31 preliminary data sheet gnd an01 power 69 gnd an02 gnd an03 gnd an07 gnd an12 gnd an23 gnd an28 gnd an31 gnd an33 gnd an34 gnd ap01 gnd ap02 gnd ap03 gnd ap04 gnd ap06 gnd ap16 gnd ap17 gnd ap33 gnd ap34 table 3. signals listed alphabetically (part 11 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 32 amcc proprietary revision 1.07 ? may 29, 2008 gpio00[gmc1txd0, gmc2txd0, rmii2txd0] ag01 system 68 gpio01[gmc1txd1, gmc2txd1, rmii2txd1] ad05 gpio02[gmc1txd2, gmc2txd2, rmii3txd0] ae04 gpio03[gmc1txd3, gmc2txd3, rmii3txd1] af01 gpio04[gmc1txd4, gmc3txd0] ae02 gpio05[gmc1txd5, gmc3txd1] ae01 gpio06[gmc1txd6, gmc3txd2] ab05 gpio07[gmc1txd7, gmc3txd3] ad03 gpio08[gmc1rxd0, gmc2rxd0, rmii2rxd0] ah04 gpio09[gmc1rxd1, gmc2rxd1, rmii2rxd1] aj05 gpio10[gmc1rxd2, gmc2rxd2, rmii3rxd0] ag06 gpio11[gmc1rxd3, gmc2rxd3, rmii3rxd1] aj02 gpio12[gmc1rxd4, gmc3rxd0] aj04 gpio13[gmc1rxd5, gmc3rxd1] ah03 gpio14[gmc1rxd6, gmc3rxd2] aj01 gpio15[gmc1rxd7, gmc3rxd3] ah01 gpio16[gmc1txer, gmc3txctl, rmii3txen] af04 gpio17[gmc1cd, gmc3rxclk, rmii3rxer] ag02 gpio18[gmc1rxer, gmc3rxctl, rmii2rxer] ag04 gpio19[gmc1txen, gmc2txctl, rmii2txen] af03 gpio20[gmc1crs, gmc3txclk, rmii2crsdv] ag03 gpio21[gmc1rxdv, gmc2rxctl, rmii3crsdv] ad04 gpio22[nfrdybusy ] c24 gpio23[nfren ] b24 gpio24[nfwen ] a24 gpio25[nfcle] f26 gpio26[nfale] a25 gpio27[irq0] d12 gpio28[irq1] e12 gpio29[irq2] f12 gpio30[perpar0][dmareq2][irq7] a20 gpio31[perpar1][dmaack2][irq8] a16 table 3. signals listed alphabetically (part 12 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 33 preliminary data sheet gpio32[perpar2][eot2/tc2][irq9] a14 system 68 gpio33[perpar3][dmareq3][irq4] f13 gpio34[uart0dcd ][uart1cts ][uart2tx] e34 gpio35[uart0dsr ][uart1rts ][uart2rx] e32 gpio36[uart0cts ][dmaack3][uart3rx] e31 gpio37[uart0rts ][eot3/tc3][uart3tx] d33 gpio38[uart0dtr ][uart1tx][irq5] d32 gpio39[uart0ri ][uart1rx][irq6] d34 gpio40[irq3] c12 gpio41[percs1 ][nfce1 ]b22 gpio42[percs2 ][nfce2 ]d25 gpio43[percs3 ][nfce3 ][dmareq1][irq10] a22 gpio44[percs4 ][dmaack1][irq11] e21 gpio45[percs5 ][eot1/tc1][irq12] d21 gpio46[peraddr05][dmareq0][irq13] b32 gpio47[peraddr06][dmaack0][irq14] c31 gpio48[peraddr07][eot0/tc0][irq15] d30 gpio49[trcbs0] h33 gpio50[trcbs1] j34 gpio51[trcbs2] h34 gpio52[trces0] l30 gpio53[trces1] l31 gpio54[trces2] k33 gpio55[trces3] l32 gpio56[trces4] k34 gpio57[trcts0] l33 gpio58[trcts1] n29 gpio59[trcts2] m31 gpio60[trcts3] l34 gpio61[trcts4] m32 gpio62[trcts5] m34 gpio63[trcts6] n31 halt h32 system 68 hisrrst b11 ddr2/1 sdram 62 iic0sclk j31 iic peripheral 67 iic0sdata h31 [iic1sclk]spiclkout k31 [iic1sdata]spido g34 table 3. signals listed alphabetically (part 13 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 34 amcc proprietary revision 1.07 ? may 29, 2008 [irq0]gpio27 d12 interrupt 67 [irq1]gpio28 e12 [irq2]gpio29 f12 [irq3]gpio40 c12 [irq4]gpio33[perpar3][dmareq3] f13 [irq5]gpio38[uart0dtr ][uart1tx] d32 [irq6]gpio39[uart0ri ][uart1rx] d34 [irq7]gpio30[perpar0][dmareq2] a20 [irq8]gpio31[perpar1][dmaack2] a16 [irq9]gpio32[perpar2][eot2/tc2] a14 [irq10]gpio43[percs3 ][nfce3 ][dmareq1] a22 [irq11]gpio44[percs4 ][dmaack1] e21 [irq12]gpio45[percs5 ][eot1/tc1] d21 [irq13]gpio46[peraddr05][dmareq0] b32 [irq14]gpio47[peraddr06][dmaack0] c31 [irq15]gpio48[peraddr07][eot0/tc0] d30 memaddr00 ak34 ddr2/1 sdram 62 memaddr01 aj33 memaddr02 aj32 memaddr03 aj34 memaddr04 ah30 memaddr05 ah31 memaddr06 ah32 memaddr07 ag31 memaddr08 ah34 memaddr09 ag32 memaddr10 ag33 memaddr11 af31 memaddr12 ag34 memaddr13 ac29 memaddr14 af32 memclkout0 ap27 ddr2/1 sdram 62 memclkout0 an27 memclkout1 ak31 memclkout1 ak32 table 3. signals listed alphabetically (part 14 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 35 preliminary data sheet memdata00 p30 ddr2/1 sdram 62 memdata01 n34 memdata02 r32 memdata03 r30 memdata04 n33 memdata05 n32 memdata06 p34 memdata07 r31 memdata08 r34 memdata09 t34 memdata10 v34 memdata11 t32 memdata12 r33 memdata13 t31 memdata14 u33 memdata15 u34 memdata16 v32 memdata17 v31 memdata18 y32 memdata19 w30 memdata20 v33 memdata21 w34 memdata22 y34 memdata23 y33 memdata24 aa33 memdata25 aa32 memdata26 ab31 memdata27 y30 memdata28 aa34 memdata29 y31 memdata30 ab33 memdata31 ab32 table 3. signals listed alphabetically (part 15 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 36 amcc proprietary revision 1.07 ? may 29, 2008 memdata32 am26 ddr2/1 sdram 62 memdata33 ap26 memdata34 ak21 memdata35 an24 memdata36 al26 memdata37 ak26 memdata38 al24 memdata39 am24 memdata40 al23 memdata41 am23 memdata42 am21 memdata43 an21 memdata44 ak23 memdata45 ap24 memdata46 ap22 memdata47 al21 memdata48 al20 memdata49 am20 memdata50 al18 memdata51 am18 memdata52 ak20 memdata53 ap21 memdata54 ap20 memdata55 ap19 memdata56 ap18 memdata57 an17 memdata58 al16 memdata59 ap15 memdata60 ak18 memdata61 an18 memdata62 am16 memdata63 ak16 memdcfdbkd am33 ddr2/1 sdram 62 memdcfdbkr am34 memodt0 ap28 ddr2/1 sdram 62 memodt1 am27 memodt2 am28 memodt3 al27 table 3. signals listed alphabetically (part 16 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 37 preliminary data sheet memvref1a aj19 ddr2/1 sdram 62 memvref1b ab29 memvref2a aj22 memvref2b t29 [nfale]gpio26 a25 nand flash 67 [nfce0 ]percs0 e24 [nfce1 ]gpio41[percs1 ]b22 [nfce2 ]gpio42[percs2 ]d25 [nfce3 ]gpio43[percs3 ][dmareq1][irq10] a22 [nfcle]gpio25 f26 [nfrdybusy ]gpio22 c24 [nfren ]gpio23 b24 [nfwen ]gpio24 a24 ov dd b05 power 69 ov dd b09 ov dd b16 ov dd b19 ov dd b26 ov dd b30 ov dd e02 ov dd e08 ov dd e13 ov dd e22 ov dd e27 ov dd e33 ov dd f11 ov dd f24 ov dd h05 ov dd h30 ov dd j02 ov dd j33 ov dd l29 ov dd p15 ov dd p20 ov dd r14 ov dd r21 pav dd t06 power 69 pav dd aa05 table 3. signals listed alphabetically (part 17 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 38 amcc proprietary revision 1.07 ? may 29, 2008 pci0ad00 d11 pci 60 pci0ad01 e11 pci0ad02 b10 pci0ad03 a10 pci0ad04 c10 pci0ad05 f10 pci0ad06 d10 pci0ad07 a09 pci0ad08 d09 pci0ad09 a08 pci0ad10 f09 pci0ad11 b08 pci0ad12 c08 pci0ad13 d08 pci0ad14 a07 pci0ad15 f08 pci0ad16 a05 pci0ad17 a04 pci0ad18 d05 pci0ad19 b04 pci0ad20 d02 pci0ad21 f04 pci0ad22 e03 pci0ad23 d03 pci0ad24 e01 pci0ad25 e04 pci0ad26 g05 pci0ad27 g04 pci0ad28 f02 pci0ad29 h06 pci0ad30 f01 pci0ad31 f05 pci0c/be0 c09 pci 60 pci0c/be1 c07 pci0c/be2 c05 pci0c/be3 f03 pci0clk k01 pci 60 pci0devsel a06 pci0frame e06 table 3. signals listed alphabetically (part 18 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 39 preliminary data sheet pci0gnt0 /req g03 pci 60 pci0gnt1 h04 pci0gnt2 g01 pci0gnt3 h03 pci0idsel d01 pci 60 pci0int j04 pci0irdy c04 pci0m66en e09 pci0par d07 pci0perr b06 pci0req0 /gnt j06 pci 60 pci0req1 h02 pci0req2 k04 pci0req3 j05 pci0reset k03 pci 60 pci0serr e07 pci0stop c06 pci0trdy d06 pcie0avreg aa01 pci express 0 61 pcie0calrn ab02 pcie0calrp ab01 pcie0refclk aa02 pcie0refclk aa03 pcie0rx0 w04 pcie0rx0 w05 pcie0tx0 w02 pcie0tx0 w01 table 3. signals listed alphabetically (part 19 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 40 amcc proprietary revision 1.07 ? may 29, 2008 pcie1avreg[srio0avreg] r05 pci express 1 61 pcie1calrn[srio0calrn] p01 pcie1calrp[srio0calrp] p02 pcie1refclk[srio0refclk] r04 pcie1refclk [srio0refclk ]r03 pcie1rx0[srio0rx0] l05 pci express 1 61 pcie1rx0 [srio0rx0 ] l04 pcie1rx1[srio0rx1] n05 pcie1rx1 [srio0rx1 ]n04 pcie1rx2[srio0rx2] t04 pcie1rx2 [srio0rx2 ]t05 pcie1rx3[srio0rx3] v05 pcie1rx3 [srio0rx3 ]v04 pcie1tx0[srio0tx0] m02 pci express 1 61 pcie1tx0 [srio0tx0 ]m01 pcie1tx1[srio0tx1] n02 pcie1tx1 [srio0tx1 ]n01 pcie1tx2[srio0tx2] t02 pcie1tx2 [srio0tx2 ]t01 pcie1tx3 [srio0tx3 ]v02 pcie1tx3[srio0tx3] v01 table 3. signals listed alphabetically (part 20 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 41 preliminary data sheet [peraddr05]gpio46[dmareq0][irq13] b32 external peripheral 66 [peraddr06]gpio47[dmaack0][irq14] c31 [peraddr07]gpio48[eot0/tc0][irq15] d30 peraddr08 a32 peraddr09 e29 peraddr10 c30 peraddr11 b31 peraddr12 a30 peraddr13 a31 peraddr14 d29 peraddr15 c29 peraddr16 a29 peraddr17 d28 peraddr18 c28 peraddr19 b29 peraddr20 c27 peraddr21 a28 peraddr22 d26 peraddr23 f27 peraddr24 b27 peraddr25 d27 peraddr26 a27 peraddr27 c26 peraddr28 a26 peraddr29 c25 peraddr30 b25 peraddr31 d24 perblast f25 external peripheral 66 perclk f23 external peripheral 66 percs0 [nfce0 ] e24 external peripheral 66 [percs1 ]gpio41[nfce1 ]b22 [percs2 ]gpio42[nfce2 ]d25 [percs3 ]gpio43[nfce3 ][dmareq1][irq10] a22 [percs4 ]gpio44[dmaack1][irq11] e21 [percs5 ]gpio45[eot1/tc1][irq12] d21 table 3. signals listed alphabetically (part 21 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 42 amcc proprietary revision 1.07 ? may 29, 2008 perdata00 c21 external peripheral 66 perdata01 b21 perdata02 a21 perdata03 e20 perdata04 d20 perdata05 c20 perdata06 d18 perdata07 b20 perdata08 e19 perdata09 d19 perdata10 e18 perdata11 c19 perdata12 a19 perdata13 c18 perdata14 b18 perdata15 a18 perdata16 d17 perdata17 b17 perdata18 a15 perdata19 b15 perdata20 e15 perdata21 c15 perdata22 d16 perdata23 d15 perdata24 e16 perdata25 c14 perdata26 e14 perdata27 d14 perdata28 b14 perdata29 a13 perdata30 b13 perdata31 c13 [perpar0]gpio30[dmareq2][irq7] a20 external peripheral 66 [perpar1]gpio31[dmaack2][irq8] a16 [perpar2]gpio32[eot2/tc2][irq9] a14 [perpar3]gpio33[dmareq3][irq4] f13 pererr d13 external peripheral 66 peroe e26 external peripheral 66 perr/w d23 external peripheral 66 table 3. signals listed alphabetically (part 22 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 43 preliminary data sheet perready c17 external peripheral 66 perwbe0 c23 external peripheral 66 perwbe1 a23 perwbe2 d22 perwbe3 c22 ras ap30 ddr2/1 sdram 62 reserved a17 other 68 reserved e17 reserved am15 reserved an15 sgmii0rxclk ak15 ethernet sgmii 0 65 sgmii0rxclk al15 sgmii0rxd an14 sgmii0rxd ap14 sgmii0txd am11 sgmii0txd an11 sgmii1rxclk al14 ethernet sgmii 1 65 sgmii1rxclk am14 sgmii1rxd an13 sgmii1rxd ap13 sgmii1txd ak11 sgmii1txd al11 sgmii2rxclk al13 ethernet sgmii 2 65 sgmii2rxclk am13 sgmii2rxd al12 sgmii2rxd am12 sgmii2txd ap10 sgmii2txd an10 sgmiitxclk aj12 sgmiitxclk ak12 table 3. signals listed alphabetically (part 23 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 44 amcc proprietary revision 1.07 ? may 29, 2008 sov dd n30 power 69 sov dd t33 sov dd w33 sov dd y21 sov dd aa20 sov dd ab30 sov dd ad29 sov dd af33 sov dd ag30 sov dd aj24 sov dd ak22 sov dd ak27 sov dd ak33 sov dd an19 sov dd an26 sov dd an30 spagnd a11 power 69 spav dd a12 spiclkout[iic1sclk] k31 serial peripheral 67 spidi k32 spido[iic1sdata] g34 table 3. signals listed alphabetically (part 24 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 45 preliminary data sheet [srio0avreg]pcie1avreg r05 serial rapid io 65 [srio0calrn]pcie1calrn p01 [srio0calrp]pcie1calrp p02 [srio0refclk]pcie1refclk r04 [srio0refclk ]pcie1refclk r03 [srio0rx0]pcie1rx0 l05 [srio0rx0 ]pcie1rx0 l04 [srio0rx1]pcie1rx1 n05 [srio0rx1 ]pcie1rx1 n04 [srio0rx2]pcie1rx2 t04 [srio0rx2 ]pcie1rx2 t05 [srio0rx3]pcie1rx3 v05 [srio0rx3 ]pcie1rx3 v04 [srio0tx0]pcie1tx0 m02 [srio0tx0 ]pcie1tx0 m01 [srio0tx1]pcie1tx1 n02 [srio0tx1 ]pcie1tx1 n01 [srio0tx2]pcie1tx2 t02 [srio0tx2 ]pcie1tx2 t01 [srio0tx3]pcie1tx3 v02 [srio0tx3 ]pcie1tx3 v01 sysclk ad02 system 68 syserr ab03 sysreset ac02 tck j29 jtag 68 tdi f34 tdo f33 testen k29 system 68 thermona am09 thermonb al10 tmrclk c11 system 68 tms g32 jtag 68 [trcbs0]gpio49 h33 trace 68 [trcbs1]gpio50 j34 [trcbs2]gpio51 h34 table 3. signals listed alphabetically (part 25 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 46 amcc proprietary revision 1.07 ? may 29, 2008 trcclk m29 trace 68 [trces0]gpio52 l30 [trces1]gpio53 l31 [trces2]gpio54 k33 [trces3]gpio55 l32 [trces4]gpio56 k34 [trcts0]gpio57 l33 trace 68 [trcts1]gpio58 n29 [trcts2]gpio59 m31 [trcts3]gpio60 l34 [trcts4]gpio61 m32 [trcts5]gpio62 m34 [trcts6]gpio63 n31 trst h29 jtag 68 uartserclk g30 [uart0cts ]gpio36[dmaack3][uart3rx] e31 uart peripheral 67 [uart0dcd ]gpio34[uart1cts ][uart2tx] e34 [uart0dsr ]gpio35[uart1rts ][uart2rx] e32 [uart0dtr ]gpio38[uart1tx][irq5] d32 [uart0ri ]gpio39[uart1rx][irq6] d34 [uart0rts ]gpio37[eot3/tc3][uart3tx] d33 uart0rx c34 uart0tx c33 [uart 1 cts ][uart0dcd ]gpio34[uart2tx] e34 uart peripheral 67 [uart 1 rts ][uart 0 dsr ]gpio35[uart2rx] e32 [uart1rx][uart0ri ]gpio39[irq6] d34 [uart1tx][uart0dtr ]gpio38[irq5] d32 [uart2rx][uart0dsr ]gpio35[uart1rts ]e32 [uart2tx][uart0dcd ]gpio34[uart1cts ]e34 [uart3rx][uart0cts ]gpio36[dmaack3] e31 [uart3tx][uart0rts ]gpio37[eot3/tc3] d33 table 3. signals listed alphabetically (part 26 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 47 preliminary data sheet v dd f14 power 69 v dd f15 v dd f17 v dd f18 v dd f20 v dd f21 v dd p17 v dd p18 v dd p29 v dd r17 v dd r18 v dd r29 v dd u14 v dd u15 v dd u20 v dd u21 v dd u29 v dd v14 v dd v15 v dd v20 v dd v21 v dd v29 v dd y06 v dd y17 v dd y18 v dd y29 v dd aa06 power 69 v dd aa17 v dd aa18 v dd aa29 v dd ab06 v dd aj14 v dd aj15 v dd aj17 v dd aj18 v dd aj20 v dd aj21 we ap32 ddr2/1 sdram 62 table 3. signals listed alphabetically (part 27 of 27) signal name ball interface group page 460gt ? ppc460gt embedded processor preliminary data sheet 48 amcc proprietary revision 1.07 ? may 29, 2008 signals in ball assignment order in the following table, only the default signal name is sh own for each ball. multiplexed or multifunction signals are marked with an asterisk (*). to determine what other signals or functions can be programmed to those balls, look up the default signal name in table 3 on page 21. 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 49 preliminary data sheet table 4. signals listed by ba ll assignment (part 1 of 9) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 gnd c01 gnd d01 pci0idsel a02 gnd b02 gnd c02 gnd d02 pci0ad20 a03 gnd b03 gnd c03 gnd d03 pci0ad23 a04 pci0ad17 b04 pci0ad19 c04 pci0irdy d04 gnd a05 pci0ad16 b05 ov dd c05 pci0/cbe2 d05 pci0ad18 a06 pci0devsel b06 pci0perr c06 pci0stop d06 pci0trdy a07 pci0ad14 b07 gnd c07 pci0c/be1 d07 pci0par a08 pci0ad09 b08 pci0ad11 c08 pci0ad12 d08 pci0ad13 a09 pci0ad07 b09 ov dd c09 pci0c/be0 d09 pci0ad08 a10 pci0ad03 b10 pci0ad02 c10 pci0ad04 d10 pci0ad06 a11 spagnd b11 hisrrst c11 tmrclk d11 pci0ad00 a12 spav dd * b12 gnd c12 gpio40 * d12 gpio27 * a13 perdata29 b13 perdata30 c13 perdata31 d13 pererr a14 gpio32 * b14 perdata28 c14 perdata25 d14 perdata27 a15 perdata18 b15 perdata19 c15 perdata21 d15 perdata23 a16 gpio31 * b16 ov dd c16 gnd d16 perdata22 a17 reserved b17 perdata17 c17 perready d17 perdata16 a18 perdata15 b18 perdata14 c18 perdata13 d18 perdata06 a19 perdata12 b19 ov dd c19 perdata11 d19 perdata09 a20 gpio30 * b20 perdata07 c20 perdata05 d20 perdata04 a21 perdata02 b21 perdata01 c21 perdata00 d21 gpio45 * a22 gpio43 * b22 gpio41 * c22 perwbe3 d22 perwbe2 a23 perwbe1 b23 gnd c23 perwbe0 d23 perr/w a24 gpio24 * b24 gpio23 * c24 gpio22 * d24 peraddr31 a25 gpio26 * b25 peraddr30 c25 peraddr29 d25 gpio42 * a26 peraddr28 b26 ov dd c26 peraddr27 d26 peraddr22 a27 peraddr26 b27 peraddr24 c27 peraddr20 d27 peraddr25 a28 peraddr21 b28 gnd c28 peraddr18 d28 peraddr17 a29 peraddr16 b29 peraddr19 c29 peraddr15 d29 peraddr14 a30 peraddr12 b30 ov dd c30 peraddr10 d30 gpio48 * a31 peraddr13 b31 peraddr11 c31 gpio47 * d31 gnd a32 peraddr08 b32 gpio46 * c32 gnd d32 gpio38 * a33 gnd b33 gnd c33 uart0tx d33 gpio37 * a34 gnd b34 gnd c34 uart0rx d34 gpio39 * 460gt ? ppc460gt embedded processor preliminary data sheet 50 amcc proprietary revision 1.07 ? may 29, 2008 e01 pci0ad24 f01 pci0ad30 g01 pci0gnt2 h01 gnd e02 ov dd f02 pci0ad28 g02 gnd h02 pci0req1 e03 pci0ad22 f03 pci0c/be3 g03 pci0gnt0 /req h03 pci0gnt3 e04 pci0ad25 f04 pci0ad21 g04 pci0ad27 h04 pci0gnt1 e05 gnd f05 pci0ad31 g05 pci0ad26 h05 ov dd e06 pci0frame f06 gnd g06 no ball h06 pci0ad29 e07 pci0serr f07 no ball g07 no ball h07 no ball e08 ov dd f08 pci0ad15 g08 no ball h08 no ball e09 pci0m66en f09 pci0ad10 g09 no ball h09 no ball e10 gnd f10 pci0ad05 g10 no ball h10 no ball e11 pci0ad01 f11 ov dd g11 no ball h11 no ball e12 gpio28 * f12 gpio29 * g12 no ball h12 no ball e13 ov dd f13 gpio33 * g13 no ball h13 no ball e14 perdata26 f14 v dd g14 no ball h14 no ball e15 perdata20 f15 v dd g15 no ball h15 no ball e16 perdata24 f16 gnd g16 no ball h16 no ball e17 reserved f17 v dd g17 no ball h17 no ball e18 perdata10 f18 v dd g18 no ball h18 no ball e19 perdata08 f19 gnd g19 no ball h19 no ball e20 perdata03 f20 v dd g20 no ball h20 no ball e21 gpio44 * f21 v dd g21 no ball h21 no ball e22 ov dd f22 extreset g22 no ball h22 no ball e23 gnd f23 perclk g23 no ball h23 no ball e24 percs0 f24 ov dd g24 no ball h24 no ball e25 gnd f25 perblast g25 no ball h25 no ball e26 peroe f26 gpio25 * g26 no ball h26 no ball e27 ov dd f27 peraddr23 g27 no ball h27 no ball e28 gnd f28 no ball g28 no ball h28 no ball e29 peraddr09 f29 gnd g29 no ball h29 trst e30 gnd f30 gnd g30 uartserclk h30 ov dd e31 gpio36 * f31 gnd g31 gnd h31 iic0sdata e32 gpio35 * f32 gnd g32 tms h32 halt e33 ov dd f33 tdo g33 gnd h33 gpio49 * e34 gpio34 * f34 tdi g34 spido * h34 gpio51 * table 4. signals listed by ba ll assignment (part 2 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 51 preliminary data sheet j01 gnd k01 pci0clk l01 agnd m01 pcie1tx0 j02 ov dd k02 gnd l02 agnd m02 pcie1tx0 j03 gnd k03 pci0reset l03 av dd m03 av dd j04 pci0int k04 pci0req2 l04 pcie1rx0 m04 agnd j05 pci0req3 k05 gnd l05 pcie1rx0 m05 av dd j06 pci0req0 /gnt k06 gnd l06 av dd m06 agnd j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 no ball l10 no ball m10 no ball j11 no ball k11 no ball l11 no ball m11 no ball j12 no ball k12 no ball l12 no ball m12 no ball j13 no ball k13 no ball l13 no ball m13 no ball j14 no ball k14 no ball l14 no ball m14 no ball j15 no ball k15 no ball l15 no ball m15 no ball j16 no ball k16 no ball l16 no ball m16 no ball j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 no ball k19 no ball l19 no ball m19 no ball j20 no ball k20 no ball l20 no ball m20 no ball j21 no ball k21 no ball l21 no ball m21 no ball j22 no ball k22 no ball l22 no ball m22 no ball j23 no ball k23 no ball l23 no ball m23 no ball j24 no ball k24 no ball l24 no ball m24 no ball j25 no ball k25 no ball l25 no ball m25 no ball j26 no ball k26 no ball l26 no ball m26 no ball j27 no ball k27 no ball l27 no ball m27 no ball j28 no ball k28 no ball l28 no ball m28 no ball j29 tck k29 testen l29 ov dd m29 trcclk j30 gnd k30 gnd l30 gpio52 * m30 gnd j31 iic0sclk k31 spiclkout * l31 gpio53 * m31 gpio59 * j32 gnd k32 spidi * l32 gpio55 * m32 gpio61 * j33 ov dd k33 gpio54 * l33 gpio57 * m33 gnd j34 gpio50 * k34 gpio56 * l34 gpio60 * m34 gpio62 * table 4. signals listed by ba ll assignment (part 3 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor preliminary data sheet 52 amcc proprietary revision 1.07 ? may 29, 2008 n01 pcie1tx1 p01 pcie1calrn r01 agnd t01 pcie1tx2 n02 pcie1tx1 p02 pcie1calrp r02 agnd t02 pcie1tx2 n03 av dd p03 agnd r03 pcie1refclk t03 av dd n04 pcie1rx1 p04 agnd r04 pcie1refclk t04 pcie1rx2 n05 pcie1rx1 p05 av dd r05 pcie1avreg t05 pcie1rx2 n06 av dd p06 agnd r06 agnd t06 pav dd n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 no ball p10 no ball r10 no ball t10 no ball n11 no ball p11 no ball r11 no ball t11 no ball n12 no ball p12 no ball r12 no ball t12 no ball n13 no ball p13 no ball r13 no ball t13 no ball n14 no ball p14 gnd r14 ov dd t14 gnd n15 no ball p15 ov dd r15 gnd t15 gnd n16 no ball p16 gnd r16 gnd t16 gnd n17 no ball p17 v dd r17 v dd t17 gnd n18 no ball p18 v dd r18 v dd t18 gnd n19 no ball p19 gnd r19 gnd t19 gnd n20 no ball p20 ov dd r20 gnd t20 gnd n21 no ball p21 gnd r21 ov dd t21 gnd n22 no ball p22 no ball r22 no ball t22 no ball n23 no ball p23 no ball r23 no ball t23 no ball n24 no ball p24 no ball r24 no ball t24 no ball n25 no ball p25 no ball r25 no ball t25 no ball n26 no ball p26 no ball r26 no ball t26 no ball n27 no ball p27 no ball r27 no ball t27 no ball n28 no ball p28 no ball r28 no ball t28 no ball n29 gpio58 * p29 v dd r29 v dd t29 memvref2b n30 sov dd p30 memdata00 r30 memdata03 t30 gnd n31 gpio63 * p31 dm0 r31 memdata07 t31 memdata13 n32 memdata05 p32 dqs0 r32 memdata02 t32 memdata11 n33 memdata04 p33 dqs0 r33 memdata12 t33 sov dd n34 memdata01 p34 memdata06 r34 memdata08 t34 memdata09 table 4. signals listed by ba ll assignment (part 4 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 53 preliminary data sheet u01 agnd v01 pcie1tx3 w01 pcie0tx0 y01 agnd u02 av dd v02 pcie1tx3 w02 pcie0tx0 y02 av dd u03 av dd v03 av dd w03 av dd y03 agnd u04 agnd v04 pcie1rx3 w04 pcie0rx0 y04 av dd u05 agnd v05 pcie1rx3 w05 pcie0rx0 y05 agnd u06 av dd v06 av dd w06 av dd y06 v dd u07 no ball v07 no ball w07 no ball y07 no ball u08 no ball v08 no ball w08 no ball y08 no ball u09 no ball v09 no ball w09 no ball y09 no ball u10 no ball v10 no ball w10 no ball y10 no ball u11 no ball v11 no ball w11 no ball y11 no ball u12 no ball v12 no ball w12 no ball y12 no ball u13 no ball v13 no ball w13 no ball y13 no ball u14 v dd v14 v dd w14 gnd y14 e1ov dd u15 v dd v15 v dd w15 gnd y15 gnd u16 gnd v16 gnd w16 gnd y16 gnd u17 gnd v17 gnd w17 gnd y17 v dd u18 gnd v18 gnd w18 gnd y18 v dd u19 gnd v19 gnd w19 gnd y19 gnd u20 v dd v20 v dd w20 gnd y20 gnd u21 v dd v21 v dd w21 gnd y21 sov dd u22 no ball v22 no ball w22 no ball y22 no ball u23 no ball v23 no ball w23 no ball y23 no ball u24 no ball v24 no ball w24 no ball y24 no ball u25 no ball v25 no ball w25 no ball y25 no ball u26 no ball v26 no ball w26 no ball y26 no ball u27 no ball v27 no ball w27 no ball y27 no ball u28 no ball v28 no ball w28 no ball y28 no ball u29 v dd v29 v dd w29 gnd y29 v dd u30 dm1 v30 dm2 w30 memdata19 y30 memdata27 u31 dqs1 v31 memdata17 w31 dqs2 y31 memdata29 u32 dqs1 v32 memdata16 w32 dqs2 y32 memdata18 u33 memdata14 v33 memdata20 w33 sov dd y33 memdata23 u34 memdata15 v34 memdata10 w34 memdata21 y34 memdata22 table 4. signals listed by ba ll assignment (part 5 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor preliminary data sheet 54 amcc proprietary revision 1.07 ? may 29, 2008 aa01 pcie0avreg ab01 pcie0calrp ac01 gnd ad01 gnd aa02 pcie0refclk ab02 pcie0calrn ac02 sysreset ad02 sysclk aa03 pcie0refclk ab03 syserr ac03 gnd ad03 gpio07 * aa04 agnd ab04 av dd ac04 gnd ad04 gpio21 * aa05 pav dd ab05 gpio06 * ac05 gnd ad05 gpio01 * aa06 v dd ab06 v dd ac06 gmc1txclk * ad06 e1ov dd aa07 no ball ab07 no ball ac07 no ball ad07 no ball aa08 no ball ab08 no ball ac08 no ball ad08 no ball aa09 no ball ab09 no ball ac09 no ball ad09 no ball aa10 no ball ab10 no ball ac10 no ball ad10 no ball aa11 no ball ab11 no ball ac11 no ball ad11 no ball aa12 no ball ab12 no ball ac12 no ball ad12 no ball aa13 no ball ab13 no ball ac13 no ball ad13 no ball aa14 gnd ab14 no ball ac14 no ball ad14 no ball aa15 e1ov dd ab15 no ball ac15 no ball ad15 no ball aa16 gnd ab16 no ball ac16 no ball ad16 no ball aa17 v dd ab17 no ball ac17 no ball ad17 no ball aa18 v dd ab18 no ball ac18 no ball ad18 no ball aa19 gnd ab19 no ball ac19 no ball ad19 no ball aa20 sov dd ab20 no ball ac20 no ball ad20 no ball aa21 gnd ab21 no ball ac21 no ball ad21 no ball aa22 no ball ab22 no ball ac22 no ball ad22 no ball aa23 no ball ab23 no ball ac23 no ball ad23 no ball aa24 no ball ab24 no ball ac24 no ball ad24 no ball aa25 no ball ab25 no ball ac25 no ball ad25 no ball aa26 no ball ab26 no ball ac26 no ball ad26 no ball aa27 no ball ab27 no ball ac27 no ball ad27 no ball aa28 no ball ab28 no ball ac28 no ball ad28 no ball aa29 v dd ab29 memvref1b ac29 memaddr13 ad29 sov dd aa30 dqs3 ab30 sov dd ac30 ecc1 ad30 ecc7 aa31 dqs3 ab31 memdata26 ac31 ecc0 ad31 ecc6 aa32 memdata25 ab32 memdata31 ac32 ecc5 ad32 dqs8 aa33 memdata24 ab33 memdata30 ac33 gnd ad33 dqs8 aa34 memdata28 ab34 dm3 ac34 ecc4 ad34 dm8 table 4. signals listed by ba ll assignment (part 6 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 55 preliminary data sheet ae01 gpio05 * af01 gpio03 * ag01 gpio00 * ah01 gpio15 * ae02 gpio04 * af02 e1ov dd ag02 gpio17 * ah02 gnd ae03 gnd af03 gpio19 * ag03 gpio20 * ah03 gpio13 * ae04 gpio02 * af04 gpio16 * ag04 gpio18 * ah04 gpio08 * ae05 gnd af05 gnd ag05 e1ov dd ah05 gmc0txd6 ae06 gmc1gtxclk * af06 gmc1rxclk * ag06 gpio10 * ah06 no ball ae07 no ball af07 no ball ag07 no ball ah07 no ball ae08 no ball af08 no ball ag08 no ball ah08 no ball ae09 no ball af09 no ball ag09 no ball ah09 no ball ae10 no ball af10 no ball ag10 no ball ah10 no ball ae11 no ball af11 no ball ag11 no ball ah11 no ball ae12 no ball af12 no ball ag12 no ball ah12 no ball ae13 no ball af13 no ball ag13 no ball ah13 no ball ae14 no ball af14 no ball ag14 no ball ah14 no ball ae15 no ball af15 no ball ag15 no ball ah15 no ball ae16 no ball af16 no ball ag16 no ball ah16 no ball ae17 no ball af17 no ball ag17 no ball ah17 no ball ae18 no ball af18 no ball ag18 no ball ah18 no ball ae19 no ball af19 no ball ag19 no ball ah19 no ball ae20 no ball af20 no ball ag20 no ball ah20 no ball ae21 no ball af21 no ball ag21 no ball ah21 no ball ae22 no ball af22 no ball ag22 no ball ah22 no ball ae23 no ball af23 no ball ag23 no ball ah23 no ball ae24 no ball af24 no ball ag24 no ball ah24 no ball ae25 no ball af25 no ball ag25 no ball ah25 no ball ae26 no ball af26 no ball ag26 no ball ah26 no ball ae27 no ball af27 no ball ag27 no ball ah27 no ball ae28 no ball af28 no ball ag28 no ball ah28 no ball ae29 clken0 af29 gnd ag29 gnd ah29 no ball ae30 gnd af30 gnd ag30 sov dd ah30 memaddr04 ae31 clken3 af31 memaddr11 ag31 memaddr07 ah31 memaddr05 ae32 ecc2 af32 memaddr14 ag32 memaddr09 ah32 memaddr06 ae33 clken2 af33 sov dd ag33 memaddr10 ah33 gnd ae34 ecc3 af34 clken1 ag34 memaddr12 ah34 memaddr08 table 4. signals listed by ba ll assignment (part 7 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor preliminary data sheet 56 amcc proprietary revision 1.07 ? may 29, 2008 aj01 gpio14 * ak01 gmcmdio * al01 gmc0txd3 am01 gmc0txd5 aj02 gpio11 * ak02 e1ov dd al02 gmc0txd2 am02 gmc0txd0 aj03 gmcmdclk * ak03 gmc0txd4 al03 gmc0txd7 am03 gnd aj04 gpio12 * ak04 gmc0txd1 al04 gnd am04 gnd aj05 gpio09 * ak05 gnd al05 gnd am05 gmc0txen aj06 gnd ak06 gnd al06 gmc0rxdv am06 gnd aj07 no ball ak07 gnd al07 gmc0crs am07 gmc0rxclk aj08 gmc0txer ak08 e1ov dd al08 gmc0rxd5 am08 gmc0rxd6 aj09 gmc0rxd3 ak09 gmc0rxd1 al09 gmc0rxd0 am09 thermona aj10 gmc0rxer ak10 gnd al10 thermonb am10 gnd aj11 e1ov dd ak11 sgmii1txd al11 sgmii1txd am11 sgmii0txd aj12 sgmiitxclk ak12 sgmiitxclk al12 sgmii2rxd am12 sgmii2rxd aj13 gnd ak13 e2ov dd al13 sgmii2rxclk am13 sgmii2rxclk aj14 v dd ak14 gnd al14 sgmii1rxclk am14 sgmii1rxclk aj15 v dd ak15 sgmii0rxclk al15 sgmii0rxclk am15 reserved aj16 gnd ak16 memdata63 al16 memdata58 am16 memdata62 aj17 v dd ak17 dqs7 al17 dqs7 am17 dm7 aj18 v dd ak18 memdata60 al18 memdata50 am18 memdata51 aj19 memvref1a ak19 gnd al19 dqs6 am19 dqs6 aj20 v dd ak20 memdata52 al20 memdata48 am20 memdata49 aj21 v dd ak21 memdata34 al21 memdata47 am21 memdata42 aj22 memvref2a ak22 sov dd al22 gnd am22 dqs5 aj23 gnd ak23 memdata44 al23 memdata40 am23 memdata41 aj24 sov dd ak24 gnd al24 memdata38 am24 memdata39 aj25 gnd ak25 gnd al25 gnd am25 dm4 aj26 gnd ak26 memdata37 al26 memdata36 am26 memdata32 aj27 gnd ak27 sov dd al27 memodt3 am27 memodt1 aj28 no ball ak28 gnd al28 banksel0 am28 memodt2 aj29 gnd ak29 gnd al29 cas am29 banksel2 aj30 gnd ak30 gnd al30 gnd am30 gnd aj31 gnd ak31 memclkout1 al31 gnd am31 ba2 aj32 memaddr02 ak32 memclkout1 al32 gnd am32 gnd aj33 memaddr01 ak33 sov dd al33 gnd am33 memdcfdbkd aj34 memaddr03 ak34 memaddr00 al34 gnd am34 memdcfdbkr table 4. signals listed by ba ll assignment (part 8 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 57 preliminary data sheet an01 gnd ap01 gnd an02 gnd ap02 gnd an03 gnd ap03 gnd an04 gmc0txclk * ap04 gnd an05 e1ov dd ap05 gmc0cd an06 gmc0gtxclk ap06 gnd an07 gnd ap07 gmc0rxd7 an08 gmc0rxd4 ap08 gmc0rxd2 an09 e1ov dd ap09 gmcrefclk an10 sgmii2txd ap10 sgmii2txd an11 sgmii0txd ap11 eavdd an12 gnd ap12 eagnd an13 sgmii1rxd ap13 sgmii1rxd an14 sgmii0rxd ap14 sgmii0rxd an15 reserved ap15 memdata59 an16 e2ov dd ap16 gnd an17 memdata57 ap17 gnd an18 memdata61 ap18 memdata56 an19 sov dd ap19 memdata55 an20 dm6 ap20 memdata54 an21 memdata43 ap21 memdata53 an22 dqs5 ap22 memdata46 an23 gnd ap23 dm5 an24 memdata35 ap24 memdata45 an25 dqs4 ap25 dqs4 an26 sov dd ap26 memdata33 an27 memclkout0 ap27 memclkout0 an28 gnd ap28 memodt0 an29 banksel3 ap29 banksel1 an30 sov dd ap30 ras an31 gnd ap31 ba1 an32 ba0 ap32 we an33 gnd ap33 gnd an34 gnd ap34 gnd table 4. signals listed by ba ll assignment (part 9 of 9) ball signal name ball signal name ball signal name ball signal name 460gt ? ppc460gt embedded processor preliminary data sheet 58 amcc proprietary revision 1.07 ? may 29, 2008 signal descriptions the ppc460gt embedded controller is packaged in a 728-ball thermally enhanced plastic ball grid array (te- pbga). the following tables describe the package level pin-out. in the table table 7 on page 60, each i/o signal is listed along with a short description of its function. active-low signals (for example, ras ) are marked with an overline. please see table 3 on page 21 for the pin (ball) number to which each signal is assigned. multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. in most cases, the signal names shown in the following table are not accom panied by signal names that might share the same pin. if you need to know what, if any, signals are multiplexed with a particular signal, look up the name in table 3 on page 21. it is expected that in any single application a part icular pin will always be prog rammed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selectio n than would otherwise be possible. multipurpose signals in addition to multiplexing, some pins such as those ca rrying the eotx/tcx signals are also multipurpose. control of which function a multipurpose pin ha s is determined by direction, register settings, and so on. both functions are shown separated by a slash (/). table 5. pin summary group no. of pins total signal pins 437 v dd 37 ov dd 23 sov dd 16 e1ov dd 10 e2ov dd 2 gnd 160 pav dd 2 av dd 18 agnd 17 eav dd 1 eagnd 1 spav dd 1 spagnd 1 total power pins 289 reserved 2 total pins 728 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 59 preliminary data sheet multimode signals in some cases (for example, ethernet) the function of a pin may vary with different modes of operation. when a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown separated by a comma. strapping pins one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during no rmal operation (see ?strapping? on page 95). note that these are not multiplexed pins since the function of the pins is not programmable. reserved pins the balls marked reserved on this chip are not functional. however, some of the reserved balls cannot be left unconnected. connect the balls shown in table 6 as indicated: table 6. non-functional ball connections ball connection am15 1k to gnd an15 1k to gnd 460gt ? ppc460gt embedded processor preliminary data sheet 60 amcc proprietary revision 1.07 ? may 29, 2008 table 7. signal functional description (part 1 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci interface pciad00:31 address/data bus (bidirectional). i/o 3.3v pci pcic0:3/be0:3 pci command/byte enables . i/o 3.3v pci pci0clk provides timing to the pci interface for pci transactions. i 3.3v pci 1 pci0devsel indicates the driving device has decoded its address as the target of the current access. i/o 3.3v pci 4 pci0frame driven by the current master to indicate beginning and duration of an access. i/o 3.3v pci 4 pci0irdy indicates initiating agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pci0trdy i ndicates the target agent?s ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pci0stop indicates the current target is requesting the master to stop the current transaction. i/o 3.3v pci 4 pci0perr reports data parity errors duri ng all pci transactions except a special cycle. i/o 3.3v pci 4 pci0serr reports address parity errors, data parity errors on the special cycle command, or other catastrophic system errors. i/o 3.3v pci 4 pci0req0 /gnt indicates to the pci arbiter that the specified agent wishes to use the bus. when the internal arbiter is enabled, input is req0. when internal arbiter is disabled, input is gnt. i3.3v pci 4 pci0req1:3 an indication to the pci arbiter t hat the specified agent wishes to use the bus. used only when internal pci arbiter enabled. i3.3v pci 4 pci0gnt0 /req indicates that the specified agent is granted access to the bus. when the internal arbiter is enabled, output is gnt0. when the internal arbiter is disabled, output is req. o3.3v pci pci0gnt1:3 indicates that the specified agent is granted access to the bus. used only when internal pci arbiter enabled. o3.3v pci pci0idsel used as a chip select during configuration read and write transactions. i3.3v pci 5 pci0int level sensitive pci interrupt. o 3.3v pci pci0m66en capable of 66mhz operation. i 3.3v pci 5 pci0par even parity across pciad00:31 and pcic0:3/be0:3 buses. i/o 3.3v pci pci0reset brings pci device registers and logic to a consistent state. o 3.3v pci 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 61 preliminary data sheet pci express interface (n = 0 and 1) pcienrefclk pcienrefclk reference clock: 100mhz differential pair. i 2.5v lvds rcvr w/term pcienavreg analog obvservation point for manufacturing test of internal voltage regulator. note: for normal operation, do not terminate. na analog pciencalrn pciencalrp connect a 1.37k 1% external calibration resistor between these two pins. na analog pcienrx0:3 pcienrx0:3 differential receive signal pairs. pcie0 is a single-channel (rx0 only) interface. pcie1 is a four-channel (rx0:3) interface. lane 0 is lsb. note: dc couple only and bias to 0v common mode. i 2.5v lvds rcvr w/term pcientx0:3 pcientx0:3 differential transmit signal pairs. pcie0 is a single-channel (tx0 only) interface. pcie1 is a four-channel (tx0:3) interface. lane 0 is lsb. note: ac couple only. o 2.5v lvds drvr w/term table 7. signal functional description (part 2 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor preliminary data sheet 62 amcc proprietary revision 1.07 ? may 29, 2008 ddr2/1 sdram interface ba0:2 bank address supporting up to eight internal banks. o 2.5v (1.8v) sstl2 dr/rcv banksel0:3 selects up to four external ddr sdram banks (a.k.a. ranks). o 2.5v (1.8v) sstl2 dr/rcv cas column address strobe. o 2.5v (1.8v) sstl2 dr/rcv clken0:3 clock enable. o 2.5v (1.8v) sstl2 dr/rcv dm0:7 dm8 memory write data byte lane masks. dm8 is the byte lane mask for the ecc byte lane. o 2.5v (1.8v) sstl2 dr/rcv dqs0:7 dqs0:7 dqs8 dqs8 differential byte lane data strobe. differential byte lane data strobe for ecc. i/o 2.5v (1.8v) sstl2 diff dr/rcv ecc0:7 ecc check bits 0:7. i/o 2.5v (1.8v) sstl2 dr/rcv memaddr00:14 memory address bus. memaddr14 is the most significant bit (msb). o 2.5v (1.8v) sstl2 dr/rcv memdata00:63 memory data bus (memdata32:63 available for ddr2 only). memdata00 is the most significant bit (msb). i/o 2.5v (1.8v) sstl2 dr/rcv memclkout0:1 memclkout0:1 subsystem clock outputs. o 2.5v (1.8v) sstl2 dr/rcv diff driver memodt0:3 ddr2 on-die termination enable (not used with ddr1). o 2.5v (1.8v) sstl2 dr/rcv ras row address strobe. o 2.5v (1.8v) sstl2 dr/rcv we write enable. o 2.5v (1.8v) sstl2 dr/rcv memvref1a:b memory voltage reference 1, a and b input. i volt ref receiver (1.25v or 0.9v) memvref2a:b memory voltage reference 2, a and b input. i volt ref driver (1.25v or 0.9v) memdcfdbkd feedback driver for i/o timing measurements. o 2.5v (1.8v) sstl2 dr/rcv memdcfdbkr feedback receiver. connect externally to memdcfdbkd. note: connect directly to memdcfdbkr. use the shortest trace length possible. do not include se ries termination or parallel termination to vtt. i 2.5v (1.8v) sstl2 dr/rcv hisrrst sdram hardware initiated self-refresh reset control. i 3.3v lvttl 1, 2 table 7. signal functional description (part 3 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 63 preliminary data sheet ethernet 0 interface gmcmdclk gmii, mii, rgmii: management data clock. o 3.3v tolerant 2.5v cmos gmcmdio gmii, mii, rgmii: transfer command and status information between mii and phy. i/o 3.3v tolerant 2.5v cmos gmcrefclk gmii, sgmii, rgmii: 125mhz reference clock for 10/100/1000mbps. i 3.3v tolerant 2.5v cmos 1, 5 gmc0gtxclk, gmc0txclk gmii 0: transmit clock. rgmii 0: transmit clock. o 3.3v tolerant 2.5v cmos gmc0txclk, rmii01refclk, smiirefclk mii 0: transmit clock. rmii 0 & 1: 50mhz reference clock for 10/100 mbps. smii: 125mhz reference clock for 10/100 mbps. i 3.3v tolerant 2.5v cmos 1, 5 gmc0txd1:0, gmc0txd1:0, rmii0txd1:0, smii1:0txd gmii/mii 0: transmit data. rgmii 0: transmit data. rmii 0: transmit data. smii 1:0: transmit data. o 3.3v tolerant 2.5v cmos gmc0txd3:2, gmc0txd3:2, rmii1txd1:0, smii3:2txd gmii/mii 0: transmit data. rgmii 0: transmit data. rmii 1: transmit data. smii 3:2: transmit data. o 3.3v tolerant 2.5v cmos gmc0txd7:4, gmc1txd3:0 gmii 0: transmit data. rgmii 1: transmit data. o 3.3v tolerant 2.5v cmos gmc0txen, gmc0txctl, rmii0txen, smiisync gmii/mii 0: transmit enable. rgmii 0: transmit control. rmii 0: transmit enable. smii: synchronizing signal. o 3.3v tolerant 2.5v cmos gmc0txer, gmc1txctl, rmii1txen gmii/mii 0: transmit error. rgmii 1: transmit control. rmii 1: transmit enable. o 3.3v tolerant 2.5v cmos gmc0cd, gmc1rxclk rmii1rxer gmii/mii 0: collision detection. rgmii 1: receive clock. rmii 1: receive error. i 3.3v tolerant 2.5v cmos 1, 5 gmc0crs, gmc1txclk, rmii0crsdv gmii/mii 0: carrier sense. rgmii 1: transmit clock. rmii 0: carrier sense/receive data valid. i/o 3.3v tolerant 2.5v cmos gmc0rxclk, gmc0rxclk gmii/mii 0: receive clock. rgmii 0: receive clock. i 3.3v tolerant 2.5v cmos 1, 5 gmc0rxd1:0, gmc0rxd1:0, rmii0rxd1:0, smii1:0rxd gmii/mii 0: receive data. rgmii 0: receive data. rmii 0: receive data. smii 1:0: receive data. i 3.3v tolerant 2.5v cmos 5 gmc0rxd3:2, gmc0rxd3:2, rmii1rxd1:0 smii3:2rxd gmii/mii 0: receive data. rgmii 0: receive data. rmii 1: receive data. smii 3:2: receive data. i 3.3v tolerant 2.5v cmos 5 table 7. signal functional description (part 4 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor preliminary data sheet 64 amcc proprietary revision 1.07 ? may 29, 2008 gmc0rxd7:4, gmc1rxd3:0 gmii/mii 0: receive data. rgmii 1: receive data. i 3.3v tolerant 2.5v cmos 5 gmc0rxdv, gmc0rxctl, rmii1crsdv gmii/mii 0: receive data valid. rgmii 0: receive control. rmii 1: carrier sense/receive data valid i 3.3v tolerant 2.5v cmos 5 gmc0rxer, gmc1rxctl, rmii0rxer gmii/mii 0: receive error. rgmii 1: receive control. rmii 0: receive error. i 3.3v tolerant 2.5v cmos 5 ethernet 1 interface gmc1gtxclk, gmc2txclk gmii 1: transmit clock. rgmii 2: transmit clock. o 3.3v tolerant 2.5v cmos gmc1txclk, rmii23refclk mii 1: transmit clock. rmii 2 & 3: 50mhz reference clock for 10/100mbps. i 3.3v tolerant 2.5v cmos 1, 5 gmc1txd1:0, gmc2txd1:0, rmii2txd1:0 gmii/mii 1: transmit data. rgmii 2: transmit data. rmii 2: transmit data. o 3.3v tolerant 2.5v cmos gmc1txd3:2, gmc2txd3:2, rmii3txd1:0 gmii/mii 1: transmit data. rgmii 2: transmit data. rmii 3: transmit data. o 3.3v tolerant 2.5v cmos gmc1txd7:4, gmc3txd3:0 gmii 1: transmit data. rgmii 3: transmit data. o 3.3v tolerant 2.5v cmos gmc1txen, gmc2txctl, rmii2txen gmii/mii 1: transmit enable. rgmii 2: transmit control. rmii 2: transmit enable. o 3.3v tolerant 2.5v cmos gmc1txer, gmc3txctl, rmii3txen gmii/mii 1: transmit error. rgmii 3: transmit control. rmii 3: transmit enable. o 3.3v tolerant 2.5v cmos gmc1cd, gmc3rxclk, rmii3rxer gmii/mii 1: collision detection. rgmii 3: receive clock. rmii 3: receive error. i 3.3v tolerant 2.5v cmos 1, 5 gmc1crs, gmc3txclk, rmii2crsdv gmii/mii 1: carrier sense. rgmii 3: transmit clock. rmii 2: carrier sense/receive data valid. i/o 3.3v tolerant 2.5v cmos gmc1rxclk, gmc2rxclk gmii/mii 1: receive clock. rgmii 2: receive clock. i 3.3v tolerant 2.5v cmos 1, 5 gmc1rxd2:0, gmc2rxd2:0, rmii2rxd1:0 gmii/mii 1: receive data. rgmii 2: receive data. rmii 2: receive data. i 3.3v tolerant 2.5v cmos gmc1rxd3:2, gmc2rxd3:2, rmii3rxd1:0 gmii/mii 1: receive data. rgmii 2: receive data. rmii 3: receive data. i 3.3v tolerant 2.5v cmos table 7. signal functional description (part 5 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 65 preliminary data sheet gmc1rxd4:7, gmc3rxd0:3 gmii/mii 1: receive data. rgmii 3: receive data. i 3.3v tolerant 2.5v cmos 5 gmc1rxdv, gmc2rxctl, rmii3crsdv gmii/mii 1: receive data valid. rgmii 2: receive control. rmii 3: carrier sense/receive data valid. i 3.3v tolerant 2.5v cmos 5 gmc1rxer, gmc3rxctl, rmii2rxer gmii/mii 1: receive error. rgmii 3: receive control. rmii 2: receive error. i 3.3v tolerant 2.5v cmos 5 ethernet sgmii gigabit interface sgmiitxclk sgmiitxclk differential transmit clock: common 625mhz to phys. o 1.8v lvds drvr w/term sgmii0:2rxclk sgmii0:2rxclk differential receive clock: 625mhz from phy. the differential receiver clock is required for sgmii. clock recovery from the differential sgmii0:2rxd signals is not supported. i 1.8v lvds rcvr w/term sgmii0:2rxd sgmii0:2rxd differential receive data. i 1.8v lvds rcvr w/term sgmii0:2txd sgmii0:2txd differential transmit data. o 1.8v lvds drvr w/term serial rapid io interface srio0refclk srio0refclk reference clock: 100mhz differential clock pair. i cml srio0rx0:3 srio0rx0:3 differential receive signal pairs. i cml srio0tx0:3 srio0tx0:3 differential transmit signal pairs. o cml srio0avreg analog observation point for manufacturing test. note: for normal operation, do not terminate. na analog srio0calrp srio0calrn attach a 1.37 k , 1% resistor between these two pins to provide a reference for both the bias currents and the impedance calibration circuitry. na analog table 7. signal functional description (part 6 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor preliminary data sheet 66 amcc proprietary revision 1.07 ? may 29, 2008 dma interface dmaack0:3 external peripheral dma acknowledge. used by the ppc460gt to indicate that data transfers have occurred. o3.3v lvttl dmareq0:3 external peripheral dma request. used by slave peripherals to indicate they are prepared to transfer data. i 3.3v lvttl 5 eot0:3/tc0:3 end of transfer/terminal count. i/o 3.3v lvttl 5 external peripheral interface peraddr05:31 peripheral address bus used by the ppc460gt. peraddr05 is the most significant bit (msb) on this bus. i/o 3.3v lvttl perdata00:31 peripheral data bus used by the ppc460gt. perdata00 is the most significant bit (msb) on this bus. i/o 3.3v lvttl perpar0:3 peripheral data bus parity used by the ppc460gt. i/o 3.3v lvttl perblast last burst transfer. used by either the peripheral c ontroller or dma controller to indicates the last transfer of a memory access. i/o 3.3v lvttl percs0:5 external peripheral devic e select. o 3.3v lvttl peroe output enable. used by either peripheral contro ller or dma controller depending upon the type of transfer involved. when the ppc460gt is the bus master, it enables the selected device to drive the bus. o3.3v lvttl perready used by a peripheral slave to i ndicate it is ready to transfer data. i 3.3v lvttl rcvr 1, 2 perr/w read/write. used by the ppc460gt as an output by either the peripheral controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. i/o 3.3v lvttl perwbe0:3 external peripheral data bus byte enables. i/o 3.3v lvttl pererr external error. used as an input to record external slave peripheral errors. i 3.3v lvttl rcvr 1, 5 extreset peripheral reset. used by sy nchronous peripheral slaves. note: the state of any external signals or clocks cannot be guaranteed until the extreset signal has been de-asserted. o3.3v lvttl perclk peripheral clock. used by sync hronous peripheral slaves. o 3.3v lvttl table 7. signal functional description (part 7 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 67 preliminary data sheet uart peripheral interface the uart interface can be configured as follows: 1. one 8-pin, where n = 0 2. two 4-pin, where n = 0 & 1 3. four 2-pin, where n = 0 & 1 & 2 & 3 uartserclk this input provides an alternative to the internally generated serial clock. it is used in case s where the allowable internally generated clock rates are not satisfactory. i 3.3v lvttl w/pull-up 1 uartnrx receive data. i 3.3v lvttl uartntx transmit data. o 3.3v lvttl uartndcd data carrier detect. i 3.3v lvttl 6 uartndsr data set ready. i 3.3v lvttl 6 uartncts clear to send. i 3.3v lvttl 6 uartndtr data terminal ready. o 3.3v lvttl uartnrts request to send. o 3.3v lvttl uartnri ring indicator. i 3.3v lvttl iic peripheral interface (n = 0 and 1) iicnsclk iic0 serial clock. i/o 3.3v lvttl 1, 2 iicnsdata iic0 serial data. i/o 3.3v lvttl 2 nand flash interface nfale address latch enable. o 3.3v lvttl nfcle command latch enable. latches operational commands into the nand flash. o3.3v lvttl nfrdybusy ready/busy . indicates status of device duri ng program erase or page read. this signal is wire-or connected from all nand flash devices. i3.3v lvttl nfren read enable. data is latched on the rising edge. o3.3v lvttl nfwen write enable. data is latched on the rising edge. o3.3v lvttl nfce0:3 chip enable. o 3.3v lvttl serial peripheral interface spiclkout clock output. o 3.3v lvttl 1 spidi data input. i 3.3v lvttl w/pull-up 2 spido data output. o 3.3v lvttl interrupts interface irq0:15 external interrupt requests 0 through 15. i 3.3v lvttl 1, 5 table 7. signal functional description (part 8 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor preliminary data sheet 68 amcc proprietary revision 1.07 ? may 29, 2008 jtag interface tck test clock. i 3.3v lvttl w/pull-up 1 tdi test data in. i 3.3v lvttl w/pull-up tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl w/pull-up trst test reset. during chip power-up, this signal must be low from the start of v dd ramp-up until at least 32 sysclk cycles after v dd is stable in order to initialize the jtag controller. i 3.3v lvttl w/pull-up 5 system interface sysclk main system clock input. i 3.3v tolerant 2.5v cmos 1 syserr set to 1 when a machine check is generated. o 3.3v tolerant 2.5v cmos sysreset main system reset. external logic can drive this pin low (minimum of 16 cycles) to initiate a syst em reset. a system reset can also be initiated by software. i 3.3v tolerant 2.5v cmos 1, 2 tmrclk processor timer external input clock. i 3.3v lvttl w/pull-up 1 halt halt from external debugger. i 3.3v lvttl w/pull-up 1 testen test enable. note: do not connect for normal operation. i 3.3v lvttl w/pull-down gpio00:21 general purpose i/o. i/o 3.3v tolerant 2.5v cmos gpio22:63 general purpose i/o. i/o 3.3v lvttl thermona thermonb on-chip thermal monitor (p diffusion). on-chip thermal monitor (n diffusion). i o thermal monitor trace interface trcbs0:2 trace branch execution status. o 3.3v lvttl trcclk trace data capture clock; runs at 1/4 the frequency of the processor. o3.3v lvttl trces0:4 trace execution status is present ed every fourth processor clock cycle. o3.3v lvttl trcts0:6 additional information on trace execution and branch status. o 3.3v lvttl other reserved to avoid noise pickup problems, some of these balls must be connected in the board design as shown table 6 on page 59. otherwise, do not connect voltage, ground, or any signals to these pins. na na table 7. signal functional description (part 9 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 69 preliminary data sheet power v dd +1.25v?logic voltage. na na ov dd +3.3v?i/o voltage (except ddr sdram, and ethernet. na na sov dd +1.8v (ddr2) or +2.5v (ddr1)?i/o voltage for ddr sdram. na na e1ov dd +2.5v?i/o voltage for ethernet (except sgmii). na na e2ov dd +1.8v?i/o ethernet (sgmii). na na gnd ground for logic and i/o voltages. na na av dd +1.25v?pci-express serdes analog supply. na na pav dd +2.5v?pci-express serdes pll analog supply. na na agnd ground for av dd and pav dd .nana eav dd +2.5v?filtered analog voltage for ethernet plls. na na eagnd ground for eav dd .nana spav dd +2.5v?filtered analog voltage for system pll. na na spagnd ground for spav dd .nana table 7. signal functional description (part 10 of 10) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd or equivalent. 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k for lvttl or 8.2k for pci to ov dd or equivalent. 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 460gt ? ppc460gt embedded processor preliminary data sheet 70 amcc proprietary revision 1.07 ? may 29, 2008 device characteristics table 8. absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or beyond thes e maximum ratings can cause permanent damage to the device. none of the performance spec ification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes internal logic supply voltage v dd 0 to +1.6 v i/o supply voltage ov dd 0 to +3.6 v ethernet i/o supply voltage e1ov dd 0 to +2.7 v ethernet sgmii supply voltage e2ov dd 0 to +1.9 v ddr2 (ddr1) sdram i/o supply voltage sov dd 0 to +1.9 (+2.7v) v pci-express serdes analog supply voltage av dd 0 to +1.6 v 1 system pll analog supply voltage spav dd 0 to +2.7 v 1 ethernet pll analog supply voltage eav dd 0 to +2.7 v 1 pci-express serdes pll analog supply voltage pav dd 0 to +2.7 v 1 storage temperature range t stg ? 55 to +150 c case temperature under bias t c ? 40 to +120 c2 notes: 1. the analog voltages (av dd , eav dd , spav dd , and pav dd ) used for the on-chip functions can be derived from the logic voltages, but must be filtered before entering the ppc460gt. a separate filt er for each analog voltage, as shown below, is recommended: 2. this value is not a spec ification of the operational temperature range; it is a stress rating only. v dd c av dd l av dd l ? smt ferrite bead chip, murata blm18ag121sn1d c ? 0.1 f ceramic eav dd , spav dd , and pav dd l ? smt ferrite bead chip, murata blm15ag102sn1 c ? 1 f ceramic agnd 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 71 preliminary data sheet table 9. recommended dc operating conditions (part 1 of 2) device operation beyond the conditions specified is no t recommended. extended operat ion beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd +1.2 +1.25 +1.3 v 4 i/o supply voltage ov dd +3.15 +3.3 +3.45 v 4 ethernet 1 i/o supply voltage e1ov dd +2.4 +2.5 +2.6 v 4 ethernet 2 i/o supply voltage (sgmii) e2ov dd +1.7 +1.8 +1.9 v 4 ddr2 (ddr1) sdram i/o supply voltage sov dd +1.7 (+2.4) +1.8 (+2.5) +1.9 (+2.6) v 4 pci-express serdes analog supply voltage av dd +1.2 +1.25 +1.3 v 3 system pll analog supply voltage spav dd +2.4 +2.5 +2.6 v 3 ethernet pll analog supply voltage eav dd +2.4 +2.5 +2.6 v 3 pci-express serdes pll analog supply voltage pav dd +2.4 +2.5 +2.6 v 3 ddr2 (ddr1) sdram reference voltage sv ref 0.49sov dd 0.50sov dd 0.51sov dd v3 input logic high 3.3v lvttl and pci v ih +2.0 +3.6 v 1 input logic high 2.5v cmos, 3.3v tolerant +1.7 +3.6 v input logic high 1.8v ddr2 (2.5v ddr1) sv ref + 0.125 (0.15) 2.2 (3.0) v 2 input logic high (1.8v sgmii) +1.1 +2.2 v input logic low 3.3v lvttl and pci v il 0+0.8v1 input logic low 2.5v cmos 0 +0.7 v input logic low 1.8v ddr2 (2.5v ddr1) ? 0.3 ( ? 0.3) sv ref ? 0.125 (0.18) v2 input logic low (1.8v sgmii) +0.3 +0.8 v output logic high 3.3v lvttl and pci v oh +2.4 +3.6 v 1 output logic high 2.5v cmos +2.0 +2.7 v output logic high 1.8v ddr2 (2.5v ddr1) sov dd ? 0.95 (+1.95) sov dd v output logic high (1.8v sgmii) +1.23 +1.385 +1.534 v output logic low 3.3v lvttl and pci v ol 0+0.4v1 output logic low 2.5v cmos 0 +0.4 v output logic low 1.8v ddr2 (2.5v ddr1) 0 +0.45 v output logic low (1.8v sgmii) +0.841 +0.961 +1.081 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull-down i il2 0 (lpdl) 200 (mpul) a 5 460gt ? ppc460gt embedded processor preliminary data sheet 72 amcc proprietary revision 1.07 ? may 29, 2008 power supply sequencing all the ppc460gt i/o designs are power supply sequence independent. there is no requirement that the power supplies power up in any particular order. the following items are power sequence considerations: ? logic power (v dd ) is applied before the i/o supply voltages: the i/os include internal supply sequencing circuitry which ensures the output of the receiver connecte d to internal chip logic is 0 until the i/o power is applied. when the logic power is on and the i/o power supplies are off, the i/o logic connected to the associated ball neither sinks or sources significant curren t unless influenced by an internal pull-up or pull-down resistor. while the i/o supply is ramp ing, the state of the i/o ball is not predictable. this power sequence is not destructive to the i/os or internal logic and does not cause any functional problems. ? i/o power is applied before the logic power is applied: the output driver (connected the balls) comes up in an unknown state (driving 1, driving 0, or tri-state) until th e internal logic voltage is stable within normal operating range. this power sequence is not destructive to the i/os or internal logic and does not cause any functional problems. ? external voltage should not be applied to the chip i/o balls before the associated i/o power supply voltage is applied to the chip. ? a chip power-down cycle must comp lete (all i/o supply voltages and vdd are below +0.4v) before a new power-up cycle is started ? during a power-up cycle, sysreset and trst inputs should be asserted low. sysreset and trst should remain asserted until sysclo ck is stable and at least 32 sysclock ti mes after all power supplies are stable within normal operating range. failure to follow this reset sequence during the power-up cycle can result in unpredictable operation of the chip. input leakage current for pull-up i il3 ? 150 (lpdl) 0 (mpul) a 5 input max allowable overshoot 2.5v cmos v imao25 +3.9 v input max allowable overshoot 3.3v lvttl v imao33 +3.9 v input max allowable undershoot 2.5v cmos v imau25 ? 0.6 v input max allowable undershoot 3.3v lvttl v imau33 ? 0.6 v output max allowable overshoot 2.5v cmos v omao25 +3.9 v output max allowable overshoot 3.3v lvttl v omao33 +3.9 v output max allowable undershoot 2.5v cmos v omau25 ? 0.6 v output max allowable undershoot 3.3v lvttl v omau33 ? 0.6 v case temperature t c ? 40 +85 c6 notes: 1. pci drivers meet pci specifications. 2. sv ref = sov dd /2. sov dd = +1.8v for ddr2 memory or +2.5v for ddr1 memory. 3. the analog voltages used for the on-chip plls can be derived from the logic voltages, but must be filtered before entering th e ppc460gt. see ?absolute maximum ratings? on page 70. 4. lpdl is least positive down level; mpul is most positive up level. 5. case temperature, t c , is measured at top center of case surf ace with device soldered to a circuit board. table 9. recommended dc operating conditions (part 2 of 2) device operation beyond the conditions specified is no t recommended. extended operat ion beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 73 preliminary data sheet table 10. input capacitance parameter symbol maximum unit notes group 1 (3.3v tolerant 2.5v cmos i/o) c in1 5.7 pf group 2 (1.8v lvds i/o) c in2 5.0 pf group 3 (2.5v sstl2 i/o) c in3 6.4 pf group 4 (3.3v lvttl i/o) c in5 5.2 pf group 5 (pci i/o) c in6 5.7 pf group 6 (cml i/o) c in6 5.0 pf table 11. typical dc power supply requirements using ddr2 memory frequency (mhz) +1.25v supply (v dd +av dd ) +1.8v supply (sov dd +e2ov dd ) +2.5v supply (e1ov dd +eav dd + spav dd +pav dd ) +3.3v supply (ov dd ) total unit notes 600 4.67 0.67 0.07 0.27 5.68 w 1 800 4.90 0.67 0.07 0.27 5.91 w 1 1000 5.34 0.67 0.07 0.27 6.35 w 1 notes: 1. typical power is estimated and is based on a nominal voltage of v dd = +1.25v, t c = 85 c, while running linux and a test application that exercises each function with representative traffic. table 12. typical dc power supply requirements using ddr1 memory frequency (mhz) +1.25v supply (v dd +av dd ) +1.8v supply (e2ov dd ) +2.5v supply (e1ov dd +eav dd + spav dd +pav dd +sov dd ) +3.3v supply (ov dd ) total unit notes 600 4.67 0 1.18 0.27 w 1 800 4.90 0 1.18 0.27 w 1 1000 5.34 0 1.18 0.27 w 1 notes: 1. typical power is estimated and is based on a nominal voltage of v dd = +1.25v, t c = 85 c, while running linux and a test application that exercises each function with representative traffic. 460gt ? ppc460gt embedded processor preliminary data sheet 74 amcc proprietary revision 1.07 ? may 29, 2008 table 13. v dd supply power dissipation frequency (mhz) +1.2v +1.25v +1.3v unit notes 600 4.46 4.67 4.89 w 1 800 4.70 4.90 5.14 w 1 1000 5.15 5.34 5.60 w 1 notes: 1. power is estimated and is based on v dd specified in the table and t c = 85 c, while running linux and a te st application that exercises each function with representative traffic. table 14. dc power supply loads parameter symbol typical 4 maximum 3, 5 unit notes v dd (+1.25v) active operating current i dd 4270 5800 ma ov dd (+3.3v) active operating current i odd 70 80 ma e1ov dd (+2.5v) active operating current i e1odd 30 30 ma e2ov dd (+1.8v) active operating current i e2odd 40 40 ma sov dd (+1.8v) ddr2 active operating current 2 i sodd2 360 370 ma sov dd (+2.5v) ddr1 active operating current 2 i sodd1 450 470 ma av dd (+1.25v) input current 1 i add 50 50 ma 1 eav dd (+2.5v) active operating current 1 i eadd 30 30 ma 1 pav dd (+2.5v) active operating current 1 i uadd 180 180 ma 1 spav dd (+2.5v) active operating current 1 i uadd 50 50 ma 1 notes: 1. see ?absolute maximum ratings? on page 70 for filter recommendations. 2. sov dd will be either +2.5v or +1.8v but not both. 3. the maximum current values listed above are not guaranteed to be the highest obtainable. these values are dependent on many factors including the type of applications r unning, clock rates, use of internal func tional capabilities, external interface us age, case temperature, and the power supply voltages . your specific application can produc e significantly different results. v dd (logic) current and power are primarily dependent on the applicatio ns running and the use of internal chip functions (dma, pci, ethernet, and so on ). ov dd (i/o) current and power are primarily dependent on the capaciti ve loading, frequency, and utilizat ion of the external buses. 4. typical current is estimated at 1ghz with v dd = +1.25v, ov dd = +3.3v, e1ov dd = +2.5v, sov dd = +2.5v (ddr1) or +1.8v (ddr2), and t c = +85c with a typical process. 5. maximum current is estimated at 1ghz with v dd = +1.3v, ov dd = +3.45v, e1ov dd = +2.6v, sov dd = +2.6v (ddr1) or +1.9v (ddr2), and t c = +85c, and best-case process (which drives worst-case power). 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 75 preliminary data sheet thermal management the following heat sink was used in the above thermal analysis: 35w x 35l x 15h (mm) base thickness = 1.5mm fin height = 13.5mm fin thickness = 1.0mm number of fins: 11 aluminum table 15. package thermal specifications thermal resistance values for the te-pbga package in a convection environment at ?.?w are as follows: parameter symbol airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) 300 (1.53 400 (2.04) 600 (2.55) junction-to-ambient thermal resistance without heat sink ja 13.1 11.7 10.9 10.5 10.3 10 3 junction-to-ambient thermal resistance with heat sink ja 10.3 7.3 6.1 5.6 5.4 5.1 3, 6 resistance value junction-to-case thermal resistance jc 3.5 c/w 3 junction-to-board thermal resistance jb 7.3 c/w 3 notes: 1. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. 2. t a = t c ? p ca , where t a is ambient temperature and p is power consumption. 3. t cmax = t jmax ? p jc , where t jmax is maximum junction temperature (+ 125c) and p is power consumption. 4. the preceding equations assume that the chip is mount ed on a board with at least one signal and two power planes. 5. values in the table were achieved using a jedec standard board with the following characteristics: 114.5mm x 101.6mm x 1.6mm, 4 layers. the board has 100 thermal vias (same as th e number of thermal balls on the te-pbga package). 6. values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see thermal management below), attached with a 0.1mm thickness of adhesive having a thermal conductivity of 1.3w/mk. 460gt ? ppc460gt embedded processor preliminary data sheet 76 amcc proprietary revision 1.07 ? may 29, 2008 thermal monitor thermal monitoring of the chip is accomplished using the pnp transistor ( 2) provided on the chip. the collector of the transistor is connected to ground (gnd). the emitter (thermona) and base (thermonb) are connected to chip pins. a voltage measurement (v be1 and v be2 ) across the thermona and thermonb pins at the two current values i 1 and i 2 provides the chip temperature in k according to the equation: t = (q/nk)(v be2 ? v be1 )/ln(i 2 /i 1 ) k where q = 1.602 176 5310 -19 , n = 0.99 0.05, and k = 1.380 650510 -23 . note: v be2 and v be1 should be specified in volts. i 1 and i 2 can be any units of measure provided they are the same. the small values require precision measurement and current sources. test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in table 9 on page 71. ac specifications are characterized with v dd =+1.5v, t c = +85 c and a 50pf test load as shown in the figure to the right. thermona thermonb ppc460gt i 1 , i 2 (max = 300 a) e b v be1 , v be2 note: the bias voltage v eb should be between +0.5v and +0.7v. c output pin 50pf 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 77 preliminary data sheet figure 4. timing waveform table 16. clocking specifications symbol parameter min max units notes sysclk input f c frequency 66.66 100 mhz t c period 10 15 ns t cs edge stability (cycle-to-cycle jitter) ? 0.1 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns pll vco f c frequency 600 2000 mhz t c period 0.50 1.66 ns processor (cpu) clock f c frequency 400 1000 mhz 1 t c period 1 2.5 ns memclkout and plb clock f c frequency 133.33 200 mhz t c period 5 7.5 ns t ch high time 45% of nominal period 55% of nominal period ns opb clock and perclk f c frequency 33 100 mhz t c period 10 30 ns notes: 1. the maximum supported processor clock fr equency for any part is specified in the par t number (see ?ordering and pvr informati on? on page 4). t cl t ch t c 460gt ? ppc460gt embedded processor preliminary data sheet 78 amcc proprietary revision 1.07 ? may 29, 2008 spread spectrum clocking care must be taken when using a spread spectrum cloc k generator (sscg) with the ppc460gt. this controller uses a pll for clock generation inside the chip. the accura cy with which the pll follows the sscg is referred to as tracking skew . the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc460gt the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc460gt with one or more internal clocks at thei r maximum supported frequen cy, the sscg can only lower the frequency. ? the maximum frequency de viation cannot exceed ? 1%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc460gt peripherals impose more stringent requirements. ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout signal since it also tracks the modulation. ? for pci express, the maximum spread spectrum is -0.5% , modulated between 30khz and 33khz. the ports on the two ends of a link must transmit data at a rate th at is within 600 parts per m illion (ppm) of each other at all times. this is specified to allow bit ra te clock sources with a 300ppm tolerance. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is runni ng at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure that any sscg used with the ppc460gt meets the above requirements and does not adversely affect other aspects of the system. 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 79 preliminary data sheet i/o specifications table 17. peripheral interface clock timings (part 1 of 2) parameter minimum maximum units notes pci0clk frequency ? 66.66 mhz pci0clk period 15 ? ns pci0clk high time 40% of nominal period 60% of nominal period ns pci0clk low time 40% of nominal period 60% of nominal period ns gmcmdclk frequency ? 2.5 mhz gmcmdclk period 400 ? ns gmcmdclk high time 160 ? ns gmcmdclk low time 160 ? ns gmcngtxclk frequecy 2.5 125 mhz gmcngtxclk period 8 400 ns gmcntxclk frequency 2.5 25 mhz gmcntxclk period 40 400 ns gmcntxclk high time 35% of nominal period ? ns gmcntxclk low time 35% of nominal period ? ns gmcnrxclk frequency 2.5 125 mhz gmcnrxclk period 8 400 ns gmcnrxclk high time 35% of nominal period ? ns gmcnrxclk low time 35% of nominal period ? ns gmcrefclk frequency 125 125 mhz gmcrefclk period 8 8 ns gmcrefclk high time 40% of nominal period 60% of nominal period ns gmcrefclk low time 40% of nominal period 60% of nominal period ns gmcrefclk rise time ? 1 ns gmcrefclk cycle-to-c ycle jitter ? 0.1 ns sgmiirxclk frequency 625 625 mhz rmiirefclk frequency 50 50 mhz rmiirefclk accuracy ? 50 ppm rmiirefclk period 20 20 ns rmiirefclk high time 35% of nominal period ? ns rmiirefclk low time 35% of nominal period ? ns smiirefclk frequency 125 125 mhz smiirefclk accuracy ? 100 ppm 460gt ? ppc460gt embedded processor preliminary data sheet 80 amcc proprietary revision 1.07 ? may 29, 2008 perclk frequency 33 100 mhz perclk period 10 30 ns perclk high time 50% of nominal period 66% of nominal period ns perclk low time 33% of nominal period 50% of nominal period ns spiclkout frequency ?? ?? mhz iicsclk frequency ? 400 khz tmrclk frequency ? 100 mhz tmrclk period 10 ? ns tmrclk high time 40% of nominal period 60% of nominal period ns tmrclk low time 40% of nominal period 60% of nominal period ns trcclk frequency cpu f c /4 cpu f c /4 mhz uartserclk frequency ? 1000/(2t opb 1 + 2ns) mhz 1 uartserclk period 2t opb 1 + 2 ?ns1 uartserclk high time t opb 1 +1 ?ns1 uartserclk low time t opb 1 +1 ?ns1 notes: 1. t opb is the period in ns of the opb clock. the internal opb clock runs at 1/2 t he frequency of the plb clock. table 17. peripheral interface clock timings (part 2 of 2) parameter minimum maximum units notes 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 81 preliminary data sheet figure 5. input setup and hold waveform figure 6. output delay and float timing waveform clock t is t ih min min inputs valid valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive) 460gt ? ppc460gt embedded processor preliminary data sheet 82 amcc proprietary revision 1.07 ? may 29, 2008 figure 7. input setup and hold timing waveform for rgmii signals figure 8. output delay and hold timing waveform for rgmii signals gmcnrxclk t is t ih inputs valid valid t is t ih 1.25v 1.25v min min min min rgmii 1000mb timing is with reference to the raising and falling edge of gmcnrxclk. rgmii 10/100mb timing is with reference only to the raising edge of gmcnrxclk. valid gmcntxclk outputs t oh t ov float (high-z) high (drive) low (drive) valid valid valid t oh t ov 1.25v min min max max rgmii 1000mb timing is with reference to the raising and falling edge of gmcntxclk. rgmii 10/100mb timing is with reference only to the raising edge of gmcntxclk. 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 83 preliminary data sheet table 18. i/o specifications?all speeds (part 1 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci interface pci0reset n/a n/a n/a n/a 0.5 1.5 async pci0clk dc dc na na 66mhz pci0ad00:31 2.5 0 5.5 2 0.5 1.5 pci0clk pci0c0:3/be0:3 2.4 0 6 2 0.5 1.5 pci0clk pci0par 2.5 0 5.5 2 0.5 1.5 pci0clk pci0frame 2.8 0 6 2 0.5 1.5 pci0clk pci0devsel 2.1 0 6 2 0.5 1.5 pci0clk pci0irdy 2.7 0 6 2 0.5 1.5 pci0clk pci0trdy 2.9 0 6 2 0.5 1.5 pci0clk pci0stop 2.5 0 6 2 0.5 1.5 pci0clk pci0perr 2.4 0 6 2 0.5 1.5 pci0clk pci0serr 2.1 0 6 2 0.5 1.5 pci0clk pci0idsel 2.2 0 n/a n/a na na pci0clk pci0req0:3 2.3 0 n/a n/a na na pci0clk pci0gnt0:3 n/a n/a 6 2 0.5 1.5 pci0clk pci0int n/a n/a 5.8 2 0.5 1.5 async pci express interface pcienrx0:3 pcienrx0:3 pcienrefclk pcientx0:3 pcientx0:3 pcienrefclk ethernet mii interface gmcmdio n/a n/a n/a n/a 5.51 7.23 gmcmdclk 1 gmc0:1txd3:0 n/a n/a 7 1 5.51 7.23 gmc0:1txclk gmc0:1txen n/a n/a 6 1 5.51 7.23 gmc0:1txclk gmc0:1txer n/a n/a 6 1 5.51 7.23 gmc0:1txclk gmc0:1cd 10 10 n/a n/a n/a n/a gmc0:1rxclk gmc0:1crs 10 10 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxd3:0 6 10 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxdv 5 10 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxer 6 10 n/a n/a n/a n/a gmc0:1rxclk ethernet gmii interface gmcmdio n/a n/a n/a n/a 5.51 7.23 gmcmdclk 1 gmc0:1txd7:0 n/a n/a 3 2 5.51 7.23 gmc0:1gtxclk gmc0:1txen n/a n/a 3 2 5.51 7.23 gmc0:1gtxclk gmc0:1txer n/a n/a 2 2 5.51 7.23 gmc0:1gtxclk gmc0:1cd 2 0 n/a n/a n/a n/a gmc0:1rxclk gmc0:1crs 2 0 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxd7:0 2 0 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxdv 1.9 0 n/a n/a n/a n/a gmc0:1rxclk gmc0:1rxer 1.9 0 n/a n/a n/a n/a gmc0:1rxclk 460gt ? ppc460gt embedded processor preliminary data sheet 84 amcc proprietary revision 1.07 ? may 29, 2008 ethernet rgmii interface gmcmdio n/a n/a n/a n/a 5.51 7.23 gmcmdclk 1 gmc0:3txd3:0 n/a n/a 0.5 3.5 5.51 7.23 gmc0:1txclk gmc0:3txctl n/a n/a 0.5 3.5 5.51 7.23 gmc0:1txclk gmc0:3rxd3:0 1 1 n/a n/a n/a n/a gmc0:1rxclk gmc0:3rxctl 1 1 n/a n/a n/a n/a gmc0:1rxclk ethernet sgmii interface sgmii0:2rxd sgmii0:2rxd tbd tbd n/a n/a n/a n/a sgmii0rxclk sgmii0:2txd sgmii0:2txd n/a n/a tbd tbd 3.35 3.35 sgmiitxclk ethernet smii interface gmcmdio 10 10 10 1.5 5.51 7.23 gmcmdclk smiisync na na 4.8 1 5.51 7.23 smiirefclk smii0:3txd n/a n/a 4.9 1 5.51 7.23 smiirefclk smii0:3rxd 1 1 n/a n/a n/a n/a smiirefclk ethernet rmii interface rmii0:3crsdv n/a n/a rmiirefclk rmii0:3rxd1:0 n/a n/a rmiirefclk rmii0:3txd1:0 n/a n/a 5.51 7.23 rmiirefclk rmii0:3txen n/a n/a 5.51 7.23 rmiirefclk rmii0:3er n/a n/a rmiirefclk internal peripheral interface iic0:1sdata 5 1.5 5 0 15.75 10.46 iic0:1sclk spidi 5 1.5 n/a n/a n/a n/a scpclkout spido n/a n/a 7 0 15.75 10.46 scpclkout uartndcd n/a n/a n/a n/a na na uartserclk uartndsr n/a n/a n/a n/a na na uartserclk uartncts n/a n/a n/a n/a na na uartserclk uartnrts n/a n/a n/a n/a 11.08 7.37 uartserclk uartndtr n/a n/a n/a n/a 11.08 7.37 uartserclk uartnri n/a n/a n/a n/a na na uartserclk uartnrx n/a n/a n/a n/a na na uartserclk uartntx n/a n/a n/a n/a 11.08 7.37 uartserclk interrupts interface irq0:15 nananananana jtag interface tck n/a n/a n/a n/a na na 40 mhz tdi 12.5 2 n/a n/a na na tck tdo n/a n/a 12.5 3 11.08 7.37 tck tms 12.5 2 n/a n/a na na tck trst n/a n/a n/a n/a na na async table 18. i/o specifications?all speeds (part 2 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 85 preliminary data sheet system interface sysclk n/a n/a n/a n/a na na sysreset n/a n/a n/a n/a na na async syserr n/a n/a n/a n/a 11.08 7.37 async tmrclk n/a n/a n/a n/a na na async halt n/a n/a n/a n/a na na async te s t e n n/a n/a n/a n/a na na async trace interface trcbs0:2 n/a n/a 1.5 1 11.08 7.37 trcclk trces0:4 n/a n/a 1.6 1 11.08 7.37 trcclk trcts0:6 n/a n/a 1.7 1 11.08 7.37 trcclk table 18. i/o specifications?all speeds (part 3 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) 460gt ? ppc460gt embedded processor preliminary data sheet 86 amcc proprietary revision 1.07 ? may 29, 2008 table 19. i/o specifications?400mhz to 1000mhz notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface dmareq0:3 4 1 n/a n/a na na perclk dmaack0:3 n/a n/a 5.3 1 11.08 7.37 perclk eot0:3/tc0:3 4 1 5.3 1 11.08 7.37 perclk peraddr02:31 n/a n/a 4.5 1 11.08 7.37 perclk perdata00:31 2 1 4.9 1 11.08 7.37 perclk perpar0:3 2 1 4.9 1 11.08 7.37 perclk perwbe0:3 n/a n/a 4.8 1 11.08 7.37 perclk percs0:5 n/a n/a 5.3 1 11.08 7.37 perclk perr/w n/a n/a 4.5 1 11.08 7.37 perclk peroe n/a n/a 4.5 1 11.08 7.37 perclk perready 2 1 n/a n/a n/a n/a perclk perblast n/a n/a 4.5 1 11.08 7.37 perclk pererr 2 1 n/a n/a n/a n/a perclk extreset n/a n/a n/a n/a 11.08 7.37 async nand flash interface nfce0:3 n/a n/a 5.3 1 11.08 7.37 perclk nfcle n/a n/a 5.3 1 11.08 7.37 perclk nfale n/a n/a 5.3 1 11.08 7.37 perclk nfren n/a n/a 5.3 1 11.08 7.37 perclk nfwen n/a n/a 5.3 1 11.08 7.37 perclk nfrdybusy 2 1 n/a n/a na na perclk 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 87 preliminary data sheet ddr2/1 sdram i/o specifications the ddr sdram controller times its operation using the in ternal plb clock signal and generates memclkout from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout can be advanced with respect to th e plb clock by means of the sdram0_clktr programming register. in a typical system, users advance memclkout by 90 . this depends on the specific application and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the powerpc 460gt embedded processor user?s manual ). the following ddr data is generated by means of simulation and includes logic, driver, package rlc, and lengths. it is not to be used as a circuit design recommendation. values are calculated over best case and worst case processes with speed, temperature, and voltage as follows: best case = fast process: -40 c, +1.3v worst case = slow process: +105 c, +1.2 note: in all the following ddr tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case co nditions. the signals are terminated as indicated in the figure bel ow for the ddr timing data in the following sections. figure 9. ddr sdram simulati on signal termination model ddr2 sdram on-die termination impedance setting for all ddr2 applications, the on-die termination (odt) impedance value must be set to 75 ohms in the dimm extended mode register (emr) in order to optimize th e data transmission during memory write operations. 10pf 10pf memclkout memclkout 120 50 30pf addr/ctrl/data/dqs/dm (ddr1) v tt = sov dd /2 ppc460gt addr/ctrl (ddr2) note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design will depend on many factors, including the type of memory used and the board layout. 460gt ? ppc460gt embedded processor preliminary data sheet 88 amcc proprietary revision 1.07 ? may 29, 2008 ddr sdram write operation the rising edge of memclkout aligns with the first rising edge of the dqs signal on writes. the following data is generated by means of simulation and includes logic, dr iver, package rlc, and lengths. values are calculated over best case and worst case pr ocesses with speed, junction temperature, and voltage as follows: note: in the following tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditio ns. the timing numbers in the following sections are obtained using a simulation that assumes a model as shown in figure 9 . table 20. ddr sdram output driver specifications signal path output current (ma) i/o h (maximum) i/o l (maximum) write data memdata00:63 10 10 ecc0:7 10 10 dm0:8 10 10 memclkout 10 10 memaddr00:13 10 10 ba0:2 10 10 ras 10 10 cas 10 10 we 10 10 banksel0:1 10 10 clken 10 10 dqs0:8 10 10 memodt0:1 10 10 table 21. ddr sdram write operation conditions case process speed junction temperature (c) voltage (v) best fast ? 40 +1.3 worst slow +105 +1.2 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 89 preliminary data sheet the following diagram illustrates the relationship among the signals in volved with a ddr write operation. figure 10. ddr sdram write cycle timing note: the timing data in the following tables is based on simulation runs using einstimer. dqs memdata plb clk memclkout addr/cmd t sa t ha t ds t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout t ha = hold time for address and command signals from memclkout t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq) 460gt ? ppc460gt embedded processor preliminary data sheet 90 amcc proprietary revision 1.07 ? may 29, 2008 table 22. i/o timing?ddr sdram t ds notes: 1. all of the dqs signals are re ferenced to memclkout with the dqs delay line programmed to 1 cycle. 2. clock speed is 200mhz. signal name t ds (ns) minimum maximum dqs0 4.9 5.1 dqs1 4.9 5.1 dqs2 4.9 5.1 dqs3 4.9 5.1 dqs4 4.9 5.1 dqs5 4.9 5.1 dqs6 4.9 5.1 dqs7 4.9 5.1 dqs8 4.9 5.1 table 23. i/o timing?ddr sdram t sa , and t ha notes: 1. clock speed is 200mhz. t sa and t ha are referenced to memclkout rising edge. 2. the timing in this table assumes a single registered dimm load on the outputs. 3. to obtain adjusted t sa values for lower clock frequencie s, use 1/2 of the cycle time for the lower clock frequency. 4. to obtain adjusted t ha values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency. signal name t sa (ns) t ha (ns) minimum minimum memaddr00:13 +2.3 +2.3 ba0:2 banksel0:1 clken cas ras we 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 91 preliminary data sheet ddr sdram read operation data on a read is edge a ligned with the dqs. to capture the incoming data on t he rising and falling edges, dqs is delayed by the ddr co ntroller in order to center a dqs edge on valid data. figure 11 shows the data read path of a single data bit. da ta entering on the left is captured in the stage 1 flip flops. the four flip flops in stage 1 capture a 4-beat burst on the ddr interface. data captured on the rising edge of dqs is stored in the even numbered flip flops. likewis e, data captured on the fallin g edge of dqs is stored in the odd numbered flips flops. to latch the data in stage 1, a delayed version of dqs is used. initialization software is responsible for tuning the dqs delay timing so that dqs is centered on valid data. since there is process variation between parts and possible voltage vari ations on boards, read tuning is required. fixed dqs delay values should not be used on production systems. the feedback data capture window in figure 11 selects which flip flop is used to store the data sampled by dqs. each output of this block generates a pulse to an input multiplexer. the series of four pulses selecting the input multiplexer is initiated by a fe edback signal pulse on the input of the feedback data capture window. the ddr controller calculates when to assert the feedback si gnal based on when the data should be present after a read command. the width of the feedback puls e is one ddr 1x clock period. the internal ddr 1x clock is the same frequency as memclkout0:1. the feedback signal to the feedback data capture window is adjusted for propagation delay by the fine/coarse delays and is able to automatically track variations in the ddr i/o due to supply voltage and temperature. compensation for driver/receiver variations is accomplis hed by driving and receiving the feedback signal on the external memdcfdbkd and memdcfdbkr pins. when proper ly tuned, the feedback pulse is aligned to the first dqs in a 4-beat burst such that the rising edge of dqs is nominally center ed on the feedback pulse. note: using minimum trace length, connect memdcfdbkd direct ly to memdcfdbkr the data captured in stage 1 is relative to the dqs ti ming domain and is held for four memclkout clock cycles. stage 2 samples the data in stage 1 attempting to capt ure the data in the ddr 1x domain. the on-time-sample clock from the stage 2 store block samples the stage 1 data at sample cycle t1, t2, t3 or t4. the sample cycle is either selected by initialization softw are or can be automatically selected and adjusted by the ddr controller. the stage 1 data is sampled a second time by the over sample clock at a delayed sample point. the delay between the on-time-sample and over sample clocks is the over-sampling-guard-band. table 24. i/o timing?ddr sdram write timing t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 200mhz. 3. the time values in the tabl e include 1/4 of a cycle at 200mhz. 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 1. 25 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (for example, t sd ? 1.25 + 0.25t cyc ). signal names reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 0.96 0.995 memdata08:15, dm1 dqs1 0.97 0.990 memdata16:23, dm2 dqs2 0.98 0.980 memdata24:31, dm3 dqs3 0.98 0.980 memdata32:39, dm4 dqs4 0.98 0.980 memdata40:47, dm5 dqs5 0.97 0.983 memdata48:55, dm6 dqs6 0.96 0.985 memdata56:63, dm7 dqs7 0.96 0.982 ecc0:7, dm8 dqs8 0.96 0.980 460gt ? ppc460gt embedded processor preliminary data sheet 92 amcc proprietary revision 1.07 ? may 29, 2008 the feedback pulse is sampled with the data captured by the first dqs in t he 4-beat burst. capturing the data with the feedback pulse is considered a hit. the ddr controller based on hits or mi sses by the on-time sample and over sample clocks adjust the sample cycle in order to track variations in dqs. burst data from a sample hit is passed to stage 3. in stage 3 data is synchronized to the plb clock domai n and eventually driven onto the plb bus. the data captured on the rising and fa lling dqs edges is unpacked into the correc t bit locations on the upper (0:63) and lower (64:127) plb bus. when ecc is enable, ecc checking and corrections is done after stage 3. figure 11. ddr sdram read data path ddr sdram read cycle timing the following diagram illustrates the relationship of the signals invo lved with a ddr read operation. plb bus dq programmed delay package mux read dqs c d ff: flip-flop q2 dqs (diff) ddr 1x clock mux data (x64) (x64) read fifo plb 1x clock stage 2 stage 1 stage 3 ff plb bus [0:63] [64:127] dqs rising dqs falling q3 0 2 (x64) coarse delay cycles driver rec memdcfdbkd memdcfdbkr ext feedback read start feedback data capture window ddr 1x clock stage 2 store oversampling dqs aligned cas lat delay feedback signal gen fine delay t1 t2 t3 t4 fine delay ff ff 3 1 1 0 3 edge sync edge sync upper lower signals pins ff q2_ovs ff fbk signal delay +1 compare ddr 1x clock oversampling clock read latency adjust circuit c d ff ff adjust ff q3 2 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 93 preliminary data sheet figure 12. ddr sdram memory data and dqs in the following example, the data strobes (dqs) and the dat a are shown to be coincident. there is actually a slight skew as specified by the sdram specifications, and t here can be additional skew due to loading and signal routing. it is recommended that the signal length for all of the eight dqs signals be matched. the following example shows the timing relationship betw een sdram ddr data at the input pin and storing the data in stage 1. table 25. i/o timing?ddr sdram read timing t sd and t hd 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 200mhz. 3. the time values in the table include 1/ 4 of a cycle at 200mhz (5ns x 0.25 = 1.25 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 0.75 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., t sd - 1.25 + 0.25t cyc ). signal names reference signal read data vs dqs set up t sd (ns) read data vs dqs hold t hd (ns) memdata00:07 dqs0 0.393 0311 memdata08:15 dqs1 0.398 0314 memdata16:23 dqs2 0.397 0307 memdata24:31 dqs3 0.396 0309 memdata32:39 dqs4 0.394 0291 memdata40:47 dqs5 0.395 0291 memdata48:55 dqs6 0.393 0295 memdata56:63 dqs7 0.394 0308 ecc0:7 dqs8 0.389 0306 dqs memdata t sd t hd 460gt ? ppc460gt embedded processor preliminary data sheet 94 amcc proprietary revision 1.07 ? may 29, 2008 figure 13. ddr sdram read cycle timing?example dqs at data at pin d0 d2 high low feedback d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 data out stage 2 d1 d3 ddr 1x clock ddr 2x clock memclk (diff.) data out stage 1 (0) delayed dqs data out stage 1 (2) data out stage 1 (1) output ddr 1x clock cycle memcntl pin valid store 1st data t1 t2 t3 t4 oversampling guard band in stage 2 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 95 preliminary data sheet initialization the ppc460gt provides the option for setting initial parameters based on default values or by reading them from a slave prom attached to the iic0 bus (see ?serial eeprom? be low). some of the default values can be altered by strapping on external pins (see ?strapping? below). strapping while the sysreset input pin is low (system reset), the state of cert ain i/o pins is read to enable certain default initial conditions prior to ppc460gt start-up. the actual capture instant is the nearest reference clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired defau lt conditions. these pins are used fo r strap functions only during reset. following reset they are used for normal functions. the signal names assigned to the pins for normal operation are shown in parentheses following the pin number. the following table lists the strapping pins al ong with their functions and strapping options: serial eeprom during reset, initial conditions other than those obtained from the strapping pins can be read from a rom device connected to the iic0 port. at the de-assertion of reset, if the boot strap controller is enabled, the ppc460gt sequentially reads 16b from the rom de vice on the iic0 port and sets t he sdr0_sdstp0:3 registers accordingly. the initialization settings and their default values are covered in detail in the powerpc 460gt embedded processor user?s manual user?s manual . table 26. strapping pin assignments function option pin strapping e31 (uart0cts ) e34 (uart0dcd ) e32 (uart0dsr ) serial device is disabled. ea ch of the six options (a? f) is a combination of boot source, boot-source width, and clock frequency specifications. refer to the iic bootstrap controller chapter in the ppc460gt embedded processor user?s manual for details. a 000 b 001 c 010 d 011 e 100 f 101 serial device is enabled. the option being selected is the iic0 slave address that will respond with strapping data. g (0xa8)110 h (0xa4)111 460gt ? ppc460gt embedded processor preliminary data sheet 96 amcc proprietary revision 1.07 ? may 29, 2008 revision log date version contents of modification 10/01/2007 1.00 initial creation of document. 11/20/2007 1.01 change all occurrences of perdatapar to perpar. correct signal-to-ball assignments. remove reference to l2 snooping. update i/o timing. add kasumi to security features list. 01/04/2008 1.02 implement document issue 441 including: - add rmii. - remove tape-and reel shipping option. - change available cpu speeds. 01/14/2008 1.03 change maximum case temperature from +105 c to +85 c. 01/30/2008 1.04 doc issue 450. doc issue 458. 04/14/2008 1.05 add block diagram from r/ c engineering specification. reference 802.3 ethernet spec for gmcmdio timing. remove confidential status and change advanced to preliminary. add fpu. add power/current estimates. add missing items to contents. 05/05/2008 1.06 delete sav dd voltage from analog voltage filter diagram (doc issue 503). misc. updates including doc issue 512 and 526. 05/29/2008 1.07 add power sequence information (doc issue 455). 460gt ? ppc460gt embedded processor revision 1.07 ? may 29, 2008 amcc proprietary 97 preliminary data sheet printed in the united states of america, may 29, 2008 the following are trademarks of am cc corporation in the united states, or other countries, or both: amcc other company, product, and service names may be trademarks or service marks of others. preliminary edition (may 29, 2008) this document contains information on a new product under development by amcc. amcc reserves the right to change or discontinue this product without notice. this document is a preliminary edit ion of the powerpc 460gt data sheet . make sure you are using the correct edition for the level of the product. while the information contained herein is believed to be ac curate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. the information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "as is" basis without wa rranty or indemnity of any kind, whether express or implied, including without limitati on, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. any products, services, or programs discussed in this document are sold or licensed under amcc's standard terms and conditions, copies of which may be obtained from your local amcc representative. nothing in this document shall operate as an expressed or implied license or indemnity under the intellectual property rights of amcc or third parties. without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal amcc test. therefore, the results obtained in other operating environments may vary significantly. under no circumstances will amcc be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. 460gt ? ppc460gt embedded processor preliminary data sheet 98 amcc proprietary revision 1.07 ? may 29, 2008 applied micro circuits corporation 215 moffett park drive, sunnyvale, ca 94089 phone: (408) 542-8600 ? (800) 840-6055 ? fax: (408) 542-8601 http://www.amcc.com amcc reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest availab le data sheet. please consult amcc?s term and c onditions of sale for its warranties and other terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orde rs, that the information is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, nei ther does it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2007 applied micro circuits corporation. all rights reserved. |
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